Static Timing Analysis

Project : BLE Lab 3
Build Time : 09/04/15 16:22:24
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_SampleClk(FFB) CapSense_SampleClk(FFB) 47.059 kHz 47.059 kHz N/A
CapSense_SenseClk(FFB) CapSense_SenseClk(FFB) 47.059 kHz 47.059 kHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 12.000 MHz 12.000 MHz N/A
CapSense_SampleClk CyHFCLK 47.059 kHz 47.059 kHz N/A
CapSense_SenseClk CyHFCLK 47.059 kHz 47.059 kHz N/A
PRS_Clock CyHFCLK 1.000 MHz 1.000 MHz 87.520 MHz
CyIMO CyIMO 12.000 MHz 12.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 12.000 MHz 12.000 MHz N/A
CySYSCLK CySYSCLK 12.000 MHz 12.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PRS_2:sC8:PrISMdp:u0\/cl0_comb Net_108/main_2 87.520 MHz 11.426 988.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PRS_2:sC8:PrISMdp:u0\ \PRS_2:sC8:PrISMdp:u0\/clock \PRS_2:sC8:PrISMdp:u0\/cl0_comb 5.680
Route 1 \PRS_2:cl0\ \PRS_2:sC8:PrISMdp:u0\/cl0_comb Net_108/main_2 2.236
macrocell3 U(1,0) 1 Net_108 SETUP 3.510
Clock Skew 0.000
\PRS_1:sC8:PrISMdp:u0\/cl0_comb Net_104/main_2 87.596 MHz 11.416 988.584
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PRS_1:sC8:PrISMdp:u0\ \PRS_1:sC8:PrISMdp:u0\/clock \PRS_1:sC8:PrISMdp:u0\/cl0_comb 5.680
Route 1 \PRS_1:cl0\ \PRS_1:sC8:PrISMdp:u0\/cl0_comb Net_104/main_2 2.226
macrocell1 U(0,0) 1 Net_104 SETUP 3.510
Clock Skew 0.000
\PRS_2:sC8:PrISMdp:u0\/ce0_comb Net_108/main_1 92.524 MHz 10.808 989.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \PRS_2:sC8:PrISMdp:u0\ \PRS_2:sC8:PrISMdp:u0\/clock \PRS_2:sC8:PrISMdp:u0\/ce0_comb 5.060
Route 1 \PRS_2:ce0\ \PRS_2:sC8:PrISMdp:u0\/ce0_comb Net_108/main_1 2.238
macrocell3 U(1,0) 1 Net_108 SETUP 3.510
Clock Skew 0.000
\PRS_1:sC8:PrISMdp:u0\/ce0_comb Net_104/main_1 92.601 MHz 10.799 989.201
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PRS_1:sC8:PrISMdp:u0\ \PRS_1:sC8:PrISMdp:u0\/clock \PRS_1:sC8:PrISMdp:u0\/ce0_comb 5.060
Route 1 \PRS_1:ce0\ \PRS_1:sC8:PrISMdp:u0\/ce0_comb Net_104/main_1 2.229
macrocell1 U(0,0) 1 Net_104 SETUP 3.510
Clock Skew 0.000
\PRS_1:sC8:PrISMdp:u0\/ce1_comb Net_105/main_1 92.851 MHz 10.770 989.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \PRS_1:sC8:PrISMdp:u0\ \PRS_1:sC8:PrISMdp:u0\/clock \PRS_1:sC8:PrISMdp:u0\/ce1_comb 5.030
Route 1 \PRS_1:ce1\ \PRS_1:sC8:PrISMdp:u0\/ce1_comb Net_105/main_1 2.230
macrocell2 U(0,0) 1 Net_105 SETUP 3.510
Clock Skew 0.000
\PRS_1:SyncCtl:ControlReg\/control_2 Net_105/main_0 119.832 MHz 8.345 991.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PRS_1:SyncCtl:ControlReg\ \PRS_1:SyncCtl:ControlReg\/clock \PRS_1:SyncCtl:ControlReg\/control_2 2.580
Route 1 \PRS_1:compare_type1\ \PRS_1:SyncCtl:ControlReg\/control_2 Net_105/main_0 2.255
macrocell2 U(0,0) 1 Net_105 SETUP 3.510
Clock Skew 0.000
\PRS_2:SyncCtl:ControlReg\/control_1 Net_108/main_0 119.933 MHz 8.338 991.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \PRS_2:SyncCtl:ControlReg\ \PRS_2:SyncCtl:ControlReg\/clock \PRS_2:SyncCtl:ControlReg\/control_1 2.580
Route 1 \PRS_2:compare_type0\ \PRS_2:SyncCtl:ControlReg\/control_1 Net_108/main_0 2.248
macrocell3 U(1,0) 1 Net_108 SETUP 3.510
Clock Skew 0.000
\PRS_1:SyncCtl:ControlReg\/control_1 Net_104/main_0 119.976 MHz 8.335 991.665
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PRS_1:SyncCtl:ControlReg\ \PRS_1:SyncCtl:ControlReg\/clock \PRS_1:SyncCtl:ControlReg\/control_1 2.580
Route 1 \PRS_1:compare_type0\ \PRS_1:SyncCtl:ControlReg\/control_1 Net_104/main_0 2.245
macrocell1 U(0,0) 1 Net_104 SETUP 3.510
Clock Skew 0.000
\PRS_1:SyncCtl:ControlReg\/control_0 \PRS_1:enable_final_reg\/main_0 120.019 MHz 8.332 991.668
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PRS_1:SyncCtl:ControlReg\ \PRS_1:SyncCtl:ControlReg\/clock \PRS_1:SyncCtl:ControlReg\/control_0 2.580
Route 1 \PRS_1:ctrl_enable\ \PRS_1:SyncCtl:ControlReg\/control_0 \PRS_1:enable_final_reg\/main_0 2.242
macrocell4 U(0,0) 1 \PRS_1:enable_final_reg\ SETUP 3.510
Clock Skew 0.000
\PRS_2:SyncCtl:ControlReg\/control_0 \PRS_2:enable_final_reg\/main_0 120.048 MHz 8.330 991.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \PRS_2:SyncCtl:ControlReg\ \PRS_2:SyncCtl:ControlReg\/clock \PRS_2:SyncCtl:ControlReg\/control_0 2.580
Route 1 \PRS_2:ctrl_enable\ \PRS_2:SyncCtl:ControlReg\/control_0 \PRS_2:enable_final_reg\/main_0 2.240
macrocell5 U(1,0) 1 \PRS_2:enable_final_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PRS_2:enable_final_reg\/q Net_108/clk_en 3.503
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \PRS_2:enable_final_reg\ \PRS_2:enable_final_reg\/clock_0 \PRS_2:enable_final_reg\/q 1.250
Route 1 \PRS_2:enable_final_reg\ \PRS_2:enable_final_reg\/q Net_108/clk_en 2.253
macrocell3 U(1,0) 1 Net_108 HOLD 0.000
Clock Skew 0.000
\PRS_2:enable_final_reg\/q \PRS_2:sC8:PrISMdp:u0\/clk_en 3.503
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \PRS_2:enable_final_reg\ \PRS_2:enable_final_reg\/clock_0 \PRS_2:enable_final_reg\/q 1.250
Route 1 \PRS_2:enable_final_reg\ \PRS_2:enable_final_reg\/q \PRS_2:sC8:PrISMdp:u0\/clk_en 2.253
datapathcell2 U(1,0) 1 \PRS_2:sC8:PrISMdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS_1:enable_final_reg\/q Net_104/clk_en 3.522
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,0) 1 \PRS_1:enable_final_reg\ \PRS_1:enable_final_reg\/clock_0 \PRS_1:enable_final_reg\/q 1.250
Route 1 \PRS_1:enable_final_reg\ \PRS_1:enable_final_reg\/q Net_104/clk_en 2.272
macrocell1 U(0,0) 1 Net_104 HOLD 0.000
Clock Skew 0.000
\PRS_1:enable_final_reg\/q Net_105/clk_en 3.522
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,0) 1 \PRS_1:enable_final_reg\ \PRS_1:enable_final_reg\/clock_0 \PRS_1:enable_final_reg\/q 1.250
Route 1 \PRS_1:enable_final_reg\ \PRS_1:enable_final_reg\/q Net_105/clk_en 2.272
macrocell2 U(0,0) 1 Net_105 HOLD 0.000
Clock Skew 0.000
\PRS_1:enable_final_reg\/q \PRS_1:sC8:PrISMdp:u0\/clk_en 3.522
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,0) 1 \PRS_1:enable_final_reg\ \PRS_1:enable_final_reg\/clock_0 \PRS_1:enable_final_reg\/q 1.250
Route 1 \PRS_1:enable_final_reg\ \PRS_1:enable_final_reg\/q \PRS_1:sC8:PrISMdp:u0\/clk_en 2.272
datapathcell1 U(0,0) 1 \PRS_1:sC8:PrISMdp:u0\ HOLD 0.000
Clock Skew 0.000
\PRS_2:SyncCtl:ControlReg\/control_0 \PRS_2:enable_final_reg\/main_0 4.280
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \PRS_2:SyncCtl:ControlReg\ \PRS_2:SyncCtl:ControlReg\/clock \PRS_2:SyncCtl:ControlReg\/control_0 2.040
Route 1 \PRS_2:ctrl_enable\ \PRS_2:SyncCtl:ControlReg\/control_0 \PRS_2:enable_final_reg\/main_0 2.240
macrocell5 U(1,0) 1 \PRS_2:enable_final_reg\ HOLD 0.000
Clock Skew 0.000
\PRS_1:SyncCtl:ControlReg\/control_0 \PRS_1:enable_final_reg\/main_0 4.282
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PRS_1:SyncCtl:ControlReg\ \PRS_1:SyncCtl:ControlReg\/clock \PRS_1:SyncCtl:ControlReg\/control_0 2.040
Route 1 \PRS_1:ctrl_enable\ \PRS_1:SyncCtl:ControlReg\/control_0 \PRS_1:enable_final_reg\/main_0 2.242
macrocell4 U(0,0) 1 \PRS_1:enable_final_reg\ HOLD 0.000
Clock Skew 0.000
\PRS_1:SyncCtl:ControlReg\/control_1 Net_104/main_0 4.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PRS_1:SyncCtl:ControlReg\ \PRS_1:SyncCtl:ControlReg\/clock \PRS_1:SyncCtl:ControlReg\/control_1 2.040
Route 1 \PRS_1:compare_type0\ \PRS_1:SyncCtl:ControlReg\/control_1 Net_104/main_0 2.245
macrocell1 U(0,0) 1 Net_104 HOLD 0.000
Clock Skew 0.000
\PRS_2:SyncCtl:ControlReg\/control_1 Net_108/main_0 4.288
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \PRS_2:SyncCtl:ControlReg\ \PRS_2:SyncCtl:ControlReg\/clock \PRS_2:SyncCtl:ControlReg\/control_1 2.040
Route 1 \PRS_2:compare_type0\ \PRS_2:SyncCtl:ControlReg\/control_1 Net_108/main_0 2.248
macrocell3 U(1,0) 1 Net_108 HOLD 0.000
Clock Skew 0.000
\PRS_1:SyncCtl:ControlReg\/control_2 Net_105/main_0 4.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \PRS_1:SyncCtl:ControlReg\ \PRS_1:SyncCtl:ControlReg\/clock \PRS_1:SyncCtl:ControlReg\/control_2 2.040
Route 1 \PRS_1:compare_type1\ \PRS_1:SyncCtl:ControlReg\/control_2 Net_105/main_0 2.255
macrocell2 U(0,0) 1 Net_105 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ PRS_Clock
Source Destination Delay (ns)
Net_104/q RED(0)_PAD 23.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,0) 1 Net_104 Net_104/clock_0 Net_104/q 1.250
Route 1 Net_104 Net_104/q RED(0)/pin_input 5.710
iocell3 P2[6] 1 RED(0) RED(0)/pin_input RED(0)/pad_out 16.112
Route 1 RED(0)_PAD RED(0)/pad_out RED(0)_PAD 0.000
Clock Clock path delay 0.000
Net_105/q GREEN(0)_PAD 22.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,0) 1 Net_105 Net_105/clock_0 Net_105/q 1.250
Route 1 Net_105 Net_105/q GREEN(0)/pin_input 5.400
iocell2 P3[6] 1 GREEN(0) GREEN(0)/pin_input GREEN(0)/pad_out 15.420
Route 1 GREEN(0)_PAD GREEN(0)/pad_out GREEN(0)_PAD 0.000
Clock Clock path delay 0.000
Net_108/q BLUE(0)_PAD 21.687
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 Net_108 Net_108/clock_0 Net_108/q 1.250
Route 1 Net_108 Net_108/q BLUE(0)/pin_input 5.770
iocell1 P3[7] 1 BLUE(0) BLUE(0)/pin_input BLUE(0)/pad_out 14.667
Route 1 BLUE(0)_PAD BLUE(0)/pad_out BLUE(0)_PAD 0.000
Clock Clock path delay 0.000