Static Timing Analysis

Project : BLE Bridge
Build Time : 11/29/15 00:11:42
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz N/A
UART_DEB_SCBCLK CyHFCLK 1.846 MHz 1.846 MHz N/A
SPI_SCBCLK CyHFCLK 16.000 MHz 16.000 MHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
SPI_SCBCLK(FFB) SPI_SCBCLK(FFB) 16.000 MHz 16.000 MHz N/A
UART_DEB_SCBCLK(FFB) UART_DEB_SCBCLK(FFB) 1.846 MHz 1.846 MHz N/A