\PRS_2:enable_final_reg\/q |
Net_108/clk_en |
3.503 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell5 |
U(1,0) |
1 |
\PRS_2:enable_final_reg\ |
\PRS_2:enable_final_reg\/clock_0 |
\PRS_2:enable_final_reg\/q |
1.250 |
Route |
|
1 |
\PRS_2:enable_final_reg\ |
\PRS_2:enable_final_reg\/q |
Net_108/clk_en |
2.253 |
macrocell3 |
U(1,0) |
1 |
Net_108 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_2:enable_final_reg\/q |
\PRS_2:sC8:PrISMdp:u0\/clk_en |
3.503 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell5 |
U(1,0) |
1 |
\PRS_2:enable_final_reg\ |
\PRS_2:enable_final_reg\/clock_0 |
\PRS_2:enable_final_reg\/q |
1.250 |
Route |
|
1 |
\PRS_2:enable_final_reg\ |
\PRS_2:enable_final_reg\/q |
\PRS_2:sC8:PrISMdp:u0\/clk_en |
2.253 |
datapathcell2 |
U(1,0) |
1 |
\PRS_2:sC8:PrISMdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_1:enable_final_reg\/q |
Net_104/clk_en |
3.522 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell4 |
U(0,0) |
1 |
\PRS_1:enable_final_reg\ |
\PRS_1:enable_final_reg\/clock_0 |
\PRS_1:enable_final_reg\/q |
1.250 |
Route |
|
1 |
\PRS_1:enable_final_reg\ |
\PRS_1:enable_final_reg\/q |
Net_104/clk_en |
2.272 |
macrocell1 |
U(0,0) |
1 |
Net_104 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_1:enable_final_reg\/q |
Net_105/clk_en |
3.522 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell4 |
U(0,0) |
1 |
\PRS_1:enable_final_reg\ |
\PRS_1:enable_final_reg\/clock_0 |
\PRS_1:enable_final_reg\/q |
1.250 |
Route |
|
1 |
\PRS_1:enable_final_reg\ |
\PRS_1:enable_final_reg\/q |
Net_105/clk_en |
2.272 |
macrocell2 |
U(0,0) |
1 |
Net_105 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_1:enable_final_reg\/q |
\PRS_1:sC8:PrISMdp:u0\/clk_en |
3.522 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell4 |
U(0,0) |
1 |
\PRS_1:enable_final_reg\ |
\PRS_1:enable_final_reg\/clock_0 |
\PRS_1:enable_final_reg\/q |
1.250 |
Route |
|
1 |
\PRS_1:enable_final_reg\ |
\PRS_1:enable_final_reg\/q |
\PRS_1:sC8:PrISMdp:u0\/clk_en |
2.272 |
datapathcell1 |
U(0,0) |
1 |
\PRS_1:sC8:PrISMdp:u0\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_2:SyncCtl:ControlReg\/control_0 |
\PRS_2:enable_final_reg\/main_0 |
4.280 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell2 |
U(1,0) |
1 |
\PRS_2:SyncCtl:ControlReg\ |
\PRS_2:SyncCtl:ControlReg\/clock |
\PRS_2:SyncCtl:ControlReg\/control_0 |
2.040 |
Route |
|
1 |
\PRS_2:ctrl_enable\ |
\PRS_2:SyncCtl:ControlReg\/control_0 |
\PRS_2:enable_final_reg\/main_0 |
2.240 |
macrocell5 |
U(1,0) |
1 |
\PRS_2:enable_final_reg\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_1:SyncCtl:ControlReg\/control_0 |
\PRS_1:enable_final_reg\/main_0 |
4.282 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(0,0) |
1 |
\PRS_1:SyncCtl:ControlReg\ |
\PRS_1:SyncCtl:ControlReg\/clock |
\PRS_1:SyncCtl:ControlReg\/control_0 |
2.040 |
Route |
|
1 |
\PRS_1:ctrl_enable\ |
\PRS_1:SyncCtl:ControlReg\/control_0 |
\PRS_1:enable_final_reg\/main_0 |
2.242 |
macrocell4 |
U(0,0) |
1 |
\PRS_1:enable_final_reg\ |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_1:SyncCtl:ControlReg\/control_1 |
Net_104/main_0 |
4.285 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(0,0) |
1 |
\PRS_1:SyncCtl:ControlReg\ |
\PRS_1:SyncCtl:ControlReg\/clock |
\PRS_1:SyncCtl:ControlReg\/control_1 |
2.040 |
Route |
|
1 |
\PRS_1:compare_type0\ |
\PRS_1:SyncCtl:ControlReg\/control_1 |
Net_104/main_0 |
2.245 |
macrocell1 |
U(0,0) |
1 |
Net_104 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_2:SyncCtl:ControlReg\/control_1 |
Net_108/main_0 |
4.288 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell2 |
U(1,0) |
1 |
\PRS_2:SyncCtl:ControlReg\ |
\PRS_2:SyncCtl:ControlReg\/clock |
\PRS_2:SyncCtl:ControlReg\/control_1 |
2.040 |
Route |
|
1 |
\PRS_2:compare_type0\ |
\PRS_2:SyncCtl:ControlReg\/control_1 |
Net_108/main_0 |
2.248 |
macrocell3 |
U(1,0) |
1 |
Net_108 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\PRS_1:SyncCtl:ControlReg\/control_2 |
Net_105/main_0 |
4.295 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
controlcell1 |
U(0,0) |
1 |
\PRS_1:SyncCtl:ControlReg\ |
\PRS_1:SyncCtl:ControlReg\/clock |
\PRS_1:SyncCtl:ControlReg\/control_2 |
2.040 |
Route |
|
1 |
\PRS_1:compare_type1\ |
\PRS_1:SyncCtl:ControlReg\/control_2 |
Net_105/main_0 |
2.255 |
macrocell2 |
U(0,0) |
1 |
Net_105 |
|
HOLD |
0.000 |
Clock |
|
|
|
|
Skew |
0.000 |
|