LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_unsigned.all;
 
 ENTITY shell IS
 	PORT (
 		rxdat : IN     std_logic;
 		xclk  : IN     std_logic;
 		rxstb : IN     std_logic;
 		txstb : IN     std_logic;
 		txdat : OUT    std_logic;
 		
 		clk   : IN     std_logic;
 		addr  : BUFFER std_logic_vector(15 DOWNTO 0);
 		data  : INOUT  std_logic_vector(7 DOWNTO 0);
 		rd    : BUFFER std_logic;
 		wr    : BUFFER std_logic;
 		ramcs : OUT    std_logic;
 		sevseg: OUT    std_logic_vector(6 DOWNTO 0)
 	);
 END shell;
 
 ARCHITECTURE one OF shell IS
 
 	COMPONENT addmachine1 PORT (
                 clk   : IN     std_logic;
                 addr  : BUFFER std_logic_vector(15 DOWNTO 0);
                 data  : INOUT  std_logic_vector(7 DOWNTO 0);
                 rd    : BUFFER std_logic;
                 wr    : BUFFER std_logic;
                 ramcs : OUT    std_logic;
                 sevseg: OUT    std_logic_vector(6 DOWNTO 0);
                 
                 din   : IN     std_logic_vector(15 DOWNTO 0);
                 dout  : OUT    std_logic_vector(7 DOWNTO 0);
                 dsel  : IN     std_logic_vector(1 DOWNTO 0)
 	);
 	END COMPONENT;
 
         SIGNAL din        : std_logic_vector(15 DOWNTO 0);
         SIGNAL clksel     : std_logic_vector(4 DOWNTO 0);
         SIGNAL dsel       : std_logic_vector(1 DOWNTO 0);
         SIGNAL dout       : std_logic_vector(7 DOWNTO 0);
         SIGNAL txshift    : std_logic_vector(7 DOWNTO 0);
         SIGNAL txshiftnext: std_logic_vector(7 DOWNTO 0);
         SIGNAL rxshift    : std_logic_vector(22 DOWNTO 0);
         SIGNAL clkdiv     : std_logic_vector(23 DOWNTO 0);
         SIGNAL cpuclk     : std_logic;
 BEGIN
 	u1: addmachine1 PORT MAP (
 		clk    => cpuclk,
 		addr   => addr,
 		data   => data,
 		rd     => rd,
 		wr     => wr,
 		ramcs  => ramcs,
 		sevseg => sevseg,
 
 		din    => din,
 		dout   => dout,
 		dsel   => dsel
 	);
 
 -- Drive serial interface
 	WITH txstb SELECT
 		txshiftnext <= txshift(6 DOWNTO 0)&'0' WHEN '0',
                        dout WHEN OTHERS;
 	txrx: PROCESS
 	BEGIN
 		WAIT UNTIL (xclk'event AND xclk='0');
 		rxshift <= rxshift(21 DOWNTO 0)&(NOT rxdat);
 		txshift <= txshiftnext;
 	END PROCESS txrx;
 		
 	rx: PROCESS
 	BEGIN
 		WAIT UNTIL (rxstb'event AND rxstb='1');
 		din    <= rxshift(15 DOWNTO 0);
 		dsel   <= rxshift(17 DOWNTO 16);
 		clksel <= rxshift(22 DOWNTO 18);
 	END PROCESS rx;
 	txdat <=  txshift(7);
 
 -- Run clock divider
 	PROCESS
 	BEGIN
 		WAIT UNTIL (clk'event AND clk='1');
 		clkdiv <= clkdiv + 1;
 	END PROCESS;
 	WITH clksel SELECT
 		cpuclk <= clk WHEN "00000",
 		          clkdiv(0) WHEN "00001",
 		          clkdiv(1) WHEN "00010",
 		          clkdiv(2) WHEN "00011",
 		          clkdiv(3) WHEN "00100",
 		          clkdiv(4) WHEN "00101",
 		          clkdiv(5) WHEN "00110",
 		          clkdiv(6) WHEN "00111",
 		          clkdiv(7) WHEN "01000",
 		          clkdiv(8) WHEN "01001",
 		          clkdiv(9) WHEN "01010",
 		          clkdiv(10) WHEN "01011",
 		          clkdiv(11) WHEN "01100",
 		          clkdiv(12) WHEN "01101",
 		          clkdiv(13) WHEN "01110",
 		          clkdiv(14) WHEN "01111",
 		          clkdiv(15) WHEN "10000",
 		          clkdiv(16) WHEN "10001",
 		          clkdiv(17) WHEN "10010",
 		          clkdiv(18) WHEN "10011",
 		          clkdiv(19) WHEN "10100",
 		          clkdiv(20) WHEN "10101",
 		          clkdiv(21) WHEN "10110",
 		          clkdiv(22) WHEN "10111",
 		          clkdiv(23) WHEN "11000",
 		          '0'        WHEN "11110",
 		          '1'        WHEN "11111",
 		          '0'        WHEN OTHERS;		          	
 END one;
 
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