DE-Nano FPGA Board Configuration
Pin Assignments:
Pin Assignment Table:
CLOCK
Name |
Location |
Direction |
Standard |
CLOCK_50 |
R8 |
input |
3.3-V LVTTL |
KEY
Name |
Location |
Direction |
Standard |
KEY[0] |
J15 |
input |
3.3-V LVTTL |
KEY[1] |
E1 |
input |
3.3-V LVTTL |
GPIO_0 connect to GPIO Default
Name |
Location |
Direction |
Standard |
GPIO Pin Index |
GPIO_IN[0] |
A8 |
input |
3.3-V LVTTL |
1 |
GPIO[0] |
D3 |
inout |
3.3-V LVTTL |
2 |
GPIO_IN[1] |
B8 |
input |
3.3-V LVTTL |
3 |
GPIO[1] |
C3 |
inout |
3.3-V LVTTL |
4 |
GPIO[2] |
A2 |
inout |
3.3-V LVTTL |
5 |
GPIO[3] |
A3 |
inout |
3.3-V LVTTL |
6 |
GPIO[4] |
B3 |
inout |
3.3-V LVTTL |
7 |
GPIO[5] |
B4 |
inout |
3.3-V LVTTL |
8 |
GPIO[6] |
A4 |
inout |
3.3-V LVTTL |
9 |
GPIO[7] |
B5 |
inout |
3.3-V LVTTL |
10 |
GPIO[8] |
A5 |
inout |
3.3-V LVTTL |
13 |
GPIO[9] |
D5 |
inout |
3.3-V LVTTL |
14 |
GPIO[10] |
B6 |
inout |
3.3-V LVTTL |
15 |
GPIO[11] |
A6 |
inout |
3.3-V LVTTL |
16 |
GPIO[12] |
B7 |
inout |
3.3-V LVTTL |
17 |
GPIO[13] |
D6 |
inout |
3.3-V LVTTL |
18 |
GPIO[14] |
A7 |
inout |
3.3-V LVTTL |
19 |
GPIO[15] |
C6 |
inout |
3.3-V LVTTL |
20 |
GPIO[16] |
C8 |
inout |
3.3-V LVTTL |
21 |
GPIO[17] |
E6 |
inout |
3.3-V LVTTL |
22 |
GPIO[18] |
E7 |
inout |
3.3-V LVTTL |
23 |
GPIO[19] |
D8 |
inout |
3.3-V LVTTL |
24 |
GPIO[20] |
E8 |
inout |
3.3-V LVTTL |
25 |
GPIO[21] |
F8 |
inout |
3.3-V LVTTL |
26 |
GPIO[22] |
F9 |
inout |
3.3-V LVTTL |
27 |
GPIO[23] |
E9 |
inout |
3.3-V LVTTL |
28 |
GPIO[24] |
C9 |
inout |
3.3-V LVTTL |
31 |
GPIO[25] |
D9 |
inout |
3.3-V LVTTL |
32 |
GPIO[26] |
E11 |
inout |
3.3-V LVTTL |
33 |
GPIO[27] |
E10 |
inout |
3.3-V LVTTL |
34 |
GPIO[28] |
C11 |
inout |
3.3-V LVTTL |
35 |
GPIO[29] |
B11 |
inout |
3.3-V LVTTL |
36 |
GPIO[30] |
A12 |
inout |
3.3-V LVTTL |
37 |
GPIO[31] |
D11 |
inout |
3.3-V LVTTL |
38 |
GPIO[32] |
D12 |
inout |
3.3-V LVTTL |
39 |
GPIO[33] |
B12 |
inout |
3.3-V LVTTL |
40 |