typedef enum //IRQ's from Table 7-1 { INT_CT = 0, // Core Timer Interrupt INT_CS0, // Core Software Interrupt 0 INT_CS1, // Core Software Interrupt 1 INT_INT0, // External Interrupt 0 INT_INT1, // External Interrupt 1 INT_INT2, // External Interrrupt 2 INT_INT3, // External Interrupt 3 INT_INT4, // External Interupt 4 INT_T1, // Timer1 INT_T2, // Timer2 INT_T3, // Timer3 INT_T4, // Timer4 INT_T5, // Timer5 //The INT_ICxE items and INT_ICx items have been re-ordered to fix a bug //so that they work as intended. Nov. 18, 2013. INT_IC1E, // Input Capture Error 1 INT_IC2E, // Input Capture Error 2 INT_IC3E, // Input Capture Error 3 INT_IC4E, // Input Capture Error 4 INT_IC5E, // Input Capture Error 5 //The INT_ICxE items and INT_ICx items have been re-ordered to fix a bug //so that they work as intended. Nov. 18, 2013. INT_IC1, // Input Capture 1 INT_IC2, // Input Capture 2 INT_IC3, // Input Capture 3 INT_IC4, // Input Capture 4 INT_IC5, // Input Capture 5 INT_OC1, // Output Compare 1 INT_OC2, // Output Compare 2 INT_OC3, // Output Compare 3 INT_OC4, // Output Compare 4 INT_OC5, // Output Compare 5 INT_CNA, // Change Notice, Port A INT_CNB, // Change Notice, Port B INT_CNC, // Change Notice, Port C INT_SPI1, // SPI1 Vector ==> Not in the data sheet table? INT_SPI2, // SPI2 Vector ==> Not in the data sheet table? INT_SPI1E, // SPI1 Fault INT_SPI2E, // SPI2 Fault INT_SPI1TX, // SPI1 Transfer Done INT_SPI2TX, // SPI2 Transfer Done INT_SPI1RX, // SPI1 Receive Done INT_SPI2RX, // SPI2 Receive Done INT_I2C1, // I2C1 Vector ==> Not in the data sheet table? INT_I2C2, // I2C2 Vector ==> Not in the data sheet table? INT_I2C1B, // I2C1 Bus Colision Event INT_I2C2B, // I2C2 Bus Colision Event INT_I2C1S, // I2C1 Slave Event INT_I2C2S, // I2C2 Slave Event INT_I2C1M, // I2C1 Master Event INT_I2C2M, // I2C2 Master Event INT_U1, // UART1 Vector ==> Not in the data sheet table? INT_U2, // UART2 Vector ==> Not in the data sheet table? INT_U1E, // UART1 Error Event INT_U2E, // UART2 Error Event INT_U1RX, // UART1 RX Event INT_U2RX, // UART2 RX Event INT_U1TX, // UART1 TX Event INT_U2TX, // UART2 TX Event INT_AD1, // ADC1 Convert Done INT_PMP, // Parallel Master Port INT_PMPE, // Parallel Master Port Error INT_CMP1, // Comparator 1 Interrupt INT_CMP2, // Comparator 2 Interrupt INT_CMP3, // Comparator 3 Interrupt INT_FSCM, // Fail-safe Monitor INT_FCE, // Flash Control Event INT_RTCC, // Real Time Clock INT_CTMU, // CTMU INT_DMA0, // DMA Channel 0 INT_DMA1, // DMA Channel 1 INT_DMA2, // DMA Channel 2 INT_DMA3, // DMA Channel 3 INT_USB, // USB INT_NUM // Number of available interrupt soruces and vectors }INT_SOURCE;