Events recognized by the DMA controllers: Example which starts a DMA cell transfer on timer 2 timeout DmaChnSetEventControl(dmaChn, DMA_EV_START_IRQ(_TIMER_2_IRQ)); Example which starts a DMA cell transfer on spi transmit event when there is space available in the SPI1BUF transmit buffer and new data can be written DmaChnSetEventControl(DMAchn1, DMA_EV_START_IRQ(_SPI1_TX_IRQ)); /* IRQ Numbers */ #define _CORE_TIMER_IRQ 0 #define _CORE_SOFTWARE_0_IRQ 1 #define _CORE_SOFTWARE_1_IRQ 2 #define _EXTERNAL_0_IRQ 3 #define _TIMER_1_IRQ 4 #define _INPUT_CAPTURE_ERROR_1_IRQ 5 #define _INPUT_CAPTURE_1_IRQ 6 #define _OUTPUT_COMPARE_1_IRQ 7 #define _EXTERNAL_1_IRQ 8 #define _TIMER_2_IRQ 9 #define _INPUT_CAPTURE_ERROR_2_IRQ 10 #define _INPUT_CAPTURE_2_IRQ 11 #define _OUTPUT_COMPARE_2_IRQ 12 #define _EXTERNAL_2_IRQ 13 #define _TIMER_3_IRQ 14 #define _INPUT_CAPTURE_ERROR_3_IRQ 15 #define _INPUT_CAPTURE_3_IRQ 16 #define _OUTPUT_COMPARE_3_IRQ 17 #define _EXTERNAL_3_IRQ 18 #define _TIMER_4_IRQ 19 #define _INPUT_CAPTURE_ERROR_4_IRQ 20 #define _INPUT_CAPTURE_4_IRQ 21 #define _OUTPUT_COMPARE_4_IRQ 22 #define _EXTERNAL_4_IRQ 23 #define _TIMER_5_IRQ 24 #define _INPUT_CAPTURE_ERROR_5_IRQ 25 #define _INPUT_CAPTURE_5_IRQ 26 #define _OUTPUT_COMPARE_5_IRQ 27 #define _ADC_IRQ 28 #define _FAIL_SAFE_MONITOR_IRQ 29 #define _RTCC_IRQ 30 #define _FLASH_CONTROL_IRQ 31 #define _COMPARATOR_1_IRQ 32 #define _COMPARATOR_2_IRQ 33 #define _COMPARATOR_3_IRQ 34 #define _USB_IRQ 35 #define _SPI1_ERR_IRQ 36 #define _SPI1_RX_IRQ 37 #define _SPI1_TX_IRQ 38 #define _UART1_ERR_IRQ 39 #define _UART1_RX_IRQ 40 #define _UART1_TX_IRQ 41 #define _I2C1_BUS_IRQ 42 #define _I2C1_SLAVE_IRQ 43 #define _I2C1_MASTER_IRQ 44 #define _CHANGE_NOTICE_A_IRQ 45 #define _CHANGE_NOTICE_B_IRQ 46 #define _CHANGE_NOTICE_C_IRQ 47 #define _PMP_IRQ 48 #define _PMP_ERROR_IRQ 49 #define _SPI2_ERR_IRQ 50 #define _SPI2_RX_IRQ 51 #define _SPI2_TX_IRQ 52 #define _UART2_ERR_IRQ 53 #define _UART2_RX_IRQ 54 #define _UART2_TX_IRQ 55 #define _I2C2_BUS_IRQ 56 #define _I2C2_SLAVE_IRQ 57 #define _I2C2_MASTER_IRQ 58 #define _CTMU_IRQ 59 #define _DMA0_IRQ 60 #define _DMA1_IRQ 61 #define _DMA2_IRQ 62 #define _DMA3_IRQ 63