ECE 4760: Homework 3

  1. (a) The video line time in the demo code is set to 1018 cycles. This time does not quite match the NTSC standard. Why do you think the system works?
    (b) The NTSC video signal we will generate is not interlaced. Explain what interlacing is and how our video signal differs from NTSC video.
    You may want to refer the the Stanford page or other links on the Video Generation page.
  2. The USART0 is used in SPI mode to blast out pixels at 4 MHz. This means that a new byte's worth
    of pixels must be loaded into the UDR0 every 2 microseconds. To get full credit on this lab you will
    need to fit a ADC conversion into the two microsecond gap. It is possible to do in C, but you will need
    to count cycles. Write a practice program which just reads the ADC and stores the value in an array.
    How many cycles does it take? Show the C source, the generated assembler, and the cycle count.
  3. Rewrite the ISR with the pixel blast loop unrolled. How many cycles per loop does that save you?
  4. How accurate is the ADC when run with the prescalar set to 1 MHz? Back up yor answer with references to the datasheet.

July 18, 2012