2016.02.24.15:41:28 |
Datasheet |
Overview
All Components
VGA_Char_Buffer
altera_up_avalon_video_character_buffer_with_dma 15.1
VGA_Pixel_DMA
altera_up_avalon_video_pixel_buffer_dma 15.1
Memory Map
Sys_Clk
clock_source v15.1
Parameters
clockFrequency |
50000000 |
clockFrequencyKnown |
false |
inputClockFrequency |
0 |
resetSynchronousEdges |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_Alpha_Blender
altera_up_avalon_video_alpha_blender v15.1
Parameters
mode |
Normal |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_CLK_CLOCK_RATE |
0 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_Char_Buffer
altera_up_avalon_video_character_buffer_with_dma v15.1
Parameters
vga_device |
On-board VGA DAC |
enable_transparency |
true |
color_bits |
1-bit |
resolution |
80 x 60 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_CLK_CLOCK_RATE |
0 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_Controller
altera_up_avalon_video_vga_controller v15.1
Parameters
board |
DE1-SoC |
device |
VGA Connector |
resolution |
VGA 640x480 |
underflow_flag |
false |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_CLK_CLOCK_RATE |
25000000 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_Dual_Clock_FIFO
altera_up_avalon_video_dual_clock_buffer v15.1
VGA_Alpha_Blender
|
avalon_blended_source |
VGA_Dual_Clock_FIFO |
avalon_dc_buffer_sink |
|
Sys_Clk
|
clk |
clock_stream_in |
clk_reset |
reset_stream_in |
|
VGA_PLL
|
vga_clk |
clock_stream_out |
reset_source |
reset_stream_out |
|
|
avalon_dc_buffer_source |
VGA_Controller
|
|
|
avalon_vga_sink |
Parameters
color_bits |
10 |
color_planes |
3 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_CLOCK_STREAM_IN_CLOCK_RATE |
0 |
AUTO_CLOCK_STREAM_OUT_CLOCK_RATE |
25000000 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_PLL
altera_up_avalon_video_pll v15.1
Parameters
gui_refclk |
50.0 |
refclk |
50.0 |
video_in_clk_en |
false |
camera |
5MP Digital Camera |
vga_clk_en |
true |
gui_resolution |
VGA 640x480 |
resolution |
VGA 640x480 |
lcd_clk_en |
false |
lcd |
7" LCD on VEEK-MT and MTL Module |
device_family |
CYCLONEV |
AUTO_DEVICE |
5CSEMA5F31C6 |
AUTO_DEVICE_SPEEDGRADE |
6 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_Pixel_DMA
altera_up_avalon_video_pixel_buffer_dma v15.1
Parameters
addr_mode |
X-Y |
start_address |
134217728 |
back_start_address |
134217728 |
image_width |
640 |
image_height |
480 |
color_space |
8-bit RGB |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_CLK_CLOCK_RATE |
0 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_Pixel_FIFO
altera_up_avalon_video_dual_clock_buffer v15.1
VGA_Pixel_DMA
|
avalon_pixel_source |
VGA_Pixel_FIFO |
avalon_dc_buffer_sink |
|
Sys_Clk
|
clk |
clock_stream_in |
clk |
clock_stream_out |
clk_reset |
reset_stream_in |
clk_reset |
reset_stream_out |
|
|
avalon_dc_buffer_source |
VGA_Pixel_RGB_Resampler
|
|
|
avalon_rgb_sink |
Parameters
color_bits |
8 |
color_planes |
1 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_CLOCK_STREAM_IN_CLOCK_RATE |
0 |
AUTO_CLOCK_STREAM_OUT_CLOCK_RATE |
0 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
VGA_Pixel_RGB_Resampler
altera_up_avalon_video_rgb_resampler v15.1
Parameters
input_type |
8-bit RGB |
output_type |
30-bit RGB |
alpha |
1023 |
input_bits |
8 |
input_planes |
1 |
output_bits |
10 |
output_planes |
3 |
AUTO_DEVICE_FAMILY |
CYCLONEV |
AUTO_CLK_CLOCK_RATE |
0 |
deviceFamily |
Cyclone V |
generateLegacySim |
false |
|
Software Assignments(none) |
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rendering took 0.01 seconds |