Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
The_System|rst_controller_003|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
The_System|rst_controller_003|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
The_System|rst_controller_003 33 31 0 31 1 31 31 31 0 0 0 0 0
The_System|rst_controller_002 32 30 0 30 1 30 30 30 0 0 0 0 0
The_System|rst_controller_001 32 30 0 30 1 30 30 30 0 0 0 0 0
The_System|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
The_System|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
The_System|rst_controller 33 30 0 30 2 30 30 30 0 0 0 0 0
The_System|irq_mapper_001 0 32 0 32 32 32 32 32 0 0 0 0 0
The_System|irq_mapper 2 30 0 30 32 30 30 30 0 0 0 0 0
The_System|mm_interconnect_3|vga_subsystem_pixel_dma_control_slave_translator 87 6 2 6 74 6 6 6 0 0 0 0 0
The_System|mm_interconnect_3|pixel_dma_addr_translation_master_translator 86 15 0 15 80 15 15 15 0 0 0 0 0
The_System|mm_interconnect_3 75 0 1 0 73 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_008|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_008 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_007|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_007 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_006|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_006 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_005|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_005 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_004|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_004 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_001|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter_001 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|rsp_mux_001|arb|adder 36 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|rsp_mux_001|arb 13 0 4 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|rsp_mux_001 1173 0 0 0 139 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|rsp_mux|arb|adder 36 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|rsp_mux|arb 13 0 4 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|rsp_mux 1173 0 0 0 139 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_008 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_007 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_006 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_005 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_004 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_003 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_002 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux_001 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|rsp_demux 134 4 2 4 261 4 4 4 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_008|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_008|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_008 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_007|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_007|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_007 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_006|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_006|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_006 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_005|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_005|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_005 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_004|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_004|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_004 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_003|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_003|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_003 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_002|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_002|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_002 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_001|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_001|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux_001 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_mux 263 0 0 0 132 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|cmd_demux_001 149 81 2 81 1171 81 81 81 0 0 0 0 0
The_System|mm_interconnect_2|cmd_demux 149 81 2 81 1171 81 81 81 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 17 1 0 1 8 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 16 2 0 2 8 2 2 2 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 31 0 2 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 7 0 0 0 7 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 29 5 0 5 23 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_burst_adapter 133 0 0 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|arm_a9_hps_h2f_lw_axi_master_rd_limiter 264 0 0 0 270 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|arm_a9_hps_h2f_lw_axi_master_wr_limiter 264 0 0 0 270 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_010|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_010 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_009|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_009 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_008|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_008 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_007|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_007 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_006|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_006 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_005|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_005 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_004|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_004 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_003|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_003 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_002|the_default_decode 0 18 0 18 18 18 18 18 0 0 0 0 0
The_System|mm_interconnect_2|router_002 124 0 2 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router_001|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
The_System|mm_interconnect_2|router_001 124 0 6 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|router|the_default_decode 0 13 0 13 13 13 13 13 0 0 0 0 0
The_System|mm_interconnect_2|router 124 0 6 0 131 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_agent_rsp_fifo 164 39 0 39 123 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_agent 330 39 46 39 345 39 39 39 0 0 0 0 0
The_System|mm_interconnect_2|arm_a9_hps_h2f_lw_axi_master_agent|align_address_to_size 38 0 1 0 23 0 0 0 0 0 0 0 0
The_System|mm_interconnect_2|arm_a9_hps_h2f_lw_axi_master_agent 439 95 209 95 310 95 95 95 0 0 0 0 0
The_System|mm_interconnect_2|pixel_dma_addr_translation_slave_translator 104 5 19 5 74 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|pushbuttons_s1_translator 104 6 22 6 70 6 6 6 0 0 0 0 0
The_System|mm_interconnect_2|slider_switches_s1_translator 104 6 22 6 36 6 6 6 0 0 0 0 0
The_System|mm_interconnect_2|hex3_hex0_s1_translator 104 6 22 6 70 6 6 6 0 0 0 0 0
The_System|mm_interconnect_2|leds_s1_translator 104 6 22 6 70 6 6 6 0 0 0 0 0
The_System|mm_interconnect_2|sysid_control_slave_translator 104 6 20 6 35 6 6 6 0 0 0 0 0
The_System|mm_interconnect_2|vga_subsystem_char_buffer_control_slave_translator 104 6 20 6 74 6 6 6 0 0 0 0 0
The_System|mm_interconnect_2|av_config_avalon_av_config_slave_translator 104 5 19 5 74 5 5 5 0 0 0 0 0
The_System|mm_interconnect_2|audio_subsystem_audio_slave_translator 104 6 19 6 71 6 6 6 0 0 0 0 0
The_System|mm_interconnect_2 450 0 1 0 334 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter_001|error_adapter_0 22 1 2 1 21 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter_001 22 0 0 0 21 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter|error_adapter_0 14 1 2 1 13 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|avalon_st_adapter 14 0 0 0 13 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_to_vga_subsystem_pixel_dma_master_rsp_width_adapter|check_and_align_address_to_size 47 10 2 10 34 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_to_vga_subsystem_pixel_dma_master_rsp_width_adapter 142 3 0 3 110 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_to_arm_a9_hps_h2f_axi_master_rd_rsp_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_to_arm_a9_hps_h2f_axi_master_rd_rsp_width_adapter 142 3 0 3 245 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_to_arm_a9_hps_h2f_axi_master_wr_rsp_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_to_arm_a9_hps_h2f_axi_master_wr_rsp_width_adapter 142 3 0 3 245 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_to_vga_subsystem_pixel_dma_master_rsp_width_adapter|check_and_align_address_to_size 47 10 2 10 33 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_to_vga_subsystem_pixel_dma_master_rsp_width_adapter 124 3 0 3 110 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_to_arm_a9_hps_h2f_axi_master_rd_rsp_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_to_arm_a9_hps_h2f_axi_master_rd_rsp_width_adapter 124 3 0 3 245 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_to_arm_a9_hps_h2f_axi_master_wr_rsp_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_to_arm_a9_hps_h2f_axi_master_wr_rsp_width_adapter 124 3 0 3 245 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_to_arm_a9_hps_h2f_axi_master_rd_rsp_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_to_arm_a9_hps_h2f_axi_master_rd_rsp_width_adapter 115 3 0 3 245 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_to_arm_a9_hps_h2f_axi_master_wr_rsp_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_to_arm_a9_hps_h2f_axi_master_wr_rsp_width_adapter 115 3 0 3 245 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_pixel_dma_master_to_onchip_sram_s2_cmd_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_pixel_dma_master_to_onchip_sram_s2_cmd_width_adapter 115 5 0 5 137 5 5 5 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_pixel_dma_master_to_sdram_s1_cmd_width_adapter|uncompressor 60 4 0 4 45 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_pixel_dma_master_to_sdram_s1_cmd_width_adapter 115 4 0 4 119 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_rd_to_onchip_sram_s1_cmd_width_adapter|check_and_align_address_to_size 47 10 2 10 36 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_rd_to_onchip_sram_s1_cmd_width_adapter 250 3 4 3 137 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_rd_to_sdram_s1_cmd_width_adapter|check_and_align_address_to_size 47 10 2 10 36 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_rd_to_sdram_s1_cmd_width_adapter 250 3 4 3 119 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_rd_to_vga_subsystem_char_buffer_slave_cmd_width_adapter|check_and_align_address_to_size 47 10 2 10 36 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_rd_to_vga_subsystem_char_buffer_slave_cmd_width_adapter 250 3 4 3 110 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_wr_to_onchip_sram_s1_cmd_width_adapter|check_and_align_address_to_size 47 10 2 10 36 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_wr_to_onchip_sram_s1_cmd_width_adapter 250 3 4 3 137 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_wr_to_sdram_s1_cmd_width_adapter|check_and_align_address_to_size 47 10 2 10 36 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_wr_to_sdram_s1_cmd_width_adapter 250 3 4 3 119 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_wr_to_vga_subsystem_char_buffer_slave_cmd_width_adapter|check_and_align_address_to_size 47 10 2 10 36 10 10 10 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_wr_to_vga_subsystem_char_buffer_slave_cmd_width_adapter 250 3 4 3 110 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux_002|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux_002|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux_002 221 0 0 0 111 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux_001|arb|adder 12 6 0 6 6 6 6 6 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux_001|arb 7 0 4 0 3 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux_001 735 0 0 0 247 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux|arb|adder 12 6 0 6 6 6 6 6 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux|arb 7 0 4 0 3 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|rsp_mux 735 0 0 0 247 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|rsp_demux_003 139 1 2 1 137 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|rsp_demux_002 140 4 2 4 273 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|rsp_demux_001 123 9 2 9 355 9 9 9 0 0 0 0 0
The_System|mm_interconnect_1|rsp_demux 113 4 2 4 219 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux_003 139 0 2 0 137 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux_002|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux_002|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux_002 275 0 0 0 138 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux_001|arb|adder 12 3 0 3 6 3 3 3 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux_001|arb 7 0 1 0 3 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux_001 357 0 0 0 121 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|cmd_mux 221 0 0 0 111 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|cmd_demux_002 116 4 4 4 219 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|cmd_demux_001 252 9 3 9 733 9 9 9 0 0 0 0 0
The_System|mm_interconnect_1|cmd_demux 252 9 3 9 733 9 9 9 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter 139 9 11 9 137 9 9 9 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_burst_adapter 139 0 0 0 137 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 39 0 2 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 9 0 0 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 40 5 0 5 34 5 5 5 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 139 0 0 0 137 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_burst_adapter 139 0 0 0 137 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 39 0 2 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 9 0 0 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 40 5 0 5 33 5 5 5 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 121 0 0 0 119 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_burst_adapter 121 0 0 0 119 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract 21 1 0 1 10 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub 20 2 0 2 10 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min 39 0 2 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment 9 0 0 0 9 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size 40 5 3 5 32 5 5 5 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter 112 0 0 0 110 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_burst_adapter 112 0 0 0 110 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_pixel_dma_master_limiter 222 0 0 0 223 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_rd_limiter 492 0 0 0 493 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_wr_limiter 492 0 0 0 493 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|router_006|the_default_decode 0 4 0 4 4 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|router_006 135 0 2 0 137 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|router_005|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
The_System|mm_interconnect_1|router_005 135 0 2 0 137 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|router_004|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
The_System|mm_interconnect_1|router_004 117 0 2 0 119 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|router_003|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
The_System|mm_interconnect_1|router_003 108 0 2 0 110 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|router_002|the_default_decode 0 6 0 6 6 6 6 6 0 0 0 0 0
The_System|mm_interconnect_1|router_002 108 0 4 0 110 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|router_001|the_default_decode 0 6 0 6 6 6 6 6 0 0 0 0 0
The_System|mm_interconnect_1|router_001 243 0 4 0 245 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|router|the_default_decode 0 6 0 6 6 6 6 6 0 0 0 0 0
The_System|mm_interconnect_1|router 243 0 4 0 245 0 0 0 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_agent_rsp_fifo 175 39 0 39 134 39 39 39 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_agent|uncompressor 60 1 0 1 58 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_agent 347 39 41 39 378 39 39 39 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_agent_rsp_fifo 175 39 0 39 134 39 39 39 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_agent|uncompressor 60 1 0 1 58 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_agent 347 39 41 39 378 39 39 39 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_agent_rdata_fifo 63 41 0 41 20 41 41 41 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_agent_rsp_fifo 157 39 0 39 116 39 39 39 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_agent|uncompressor 60 1 0 1 58 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_agent 279 22 25 22 307 22 22 22 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_agent_rdata_fifo 55 41 0 41 12 41 41 41 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_agent_rsp_fifo 148 39 0 39 107 39 39 39 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_agent|uncompressor 60 1 0 1 58 1 1 1 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_agent 245 13 17 13 271 13 13 13 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_pixel_dma_master_agent 158 58 99 58 116 58 58 58 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_agent|align_address_to_size 51 2 1 2 36 2 2 2 0 0 0 0 0
The_System|mm_interconnect_1|arm_a9_hps_h2f_axi_master_agent 793 199 341 199 644 199 199 199 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s2_translator 115 7 16 7 89 7 7 7 0 0 0 0 0
The_System|mm_interconnect_1|onchip_sram_s1_translator 115 7 16 7 89 7 7 7 0 0 0 0 0
The_System|mm_interconnect_1|sdram_s1_translator 80 4 7 4 64 4 4 4 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_char_buffer_slave_translator 62 5 19 5 35 5 5 5 0 0 0 0 0
The_System|mm_interconnect_1|vga_subsystem_pixel_dma_master_translator 65 21 2 21 56 21 21 21 0 0 0 0 0
The_System|mm_interconnect_1 411 0 1 0 353 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_rd_rsp_width_adapter 168 3 2 3 127 3 3 3 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_wr_rsp_width_adapter 168 3 2 3 127 3 3 3 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_rd_cmd_width_adapter|uncompressor 58 4 0 4 44 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_rd_cmd_width_adapter 132 4 0 4 163 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_wr_cmd_width_adapter|uncompressor 58 4 0 4 44 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_wr_cmd_width_adapter 132 4 0 4 163 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux_002|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux_002|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux_002 255 0 0 0 128 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux_001|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux_001|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux_001 255 0 0 0 128 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux|arb|adder 8 4 0 4 4 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux|arb 6 0 4 0 2 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|rsp_mux 255 0 0 0 128 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|rsp_demux_001 131 9 2 9 379 9 9 9 0 0 0 0 0
The_System|mm_interconnect_0|rsp_demux 131 9 2 9 379 9 9 9 0 0 0 0 0
The_System|mm_interconnect_0|cmd_mux_001|arb|adder 12 3 0 3 6 3 3 3 0 0 0 0 0
The_System|mm_interconnect_0|cmd_mux_001|arb 7 0 1 0 3 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|cmd_mux_001 381 0 0 0 129 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|cmd_mux|arb|adder 12 3 0 3 6 3 3 3 0 0 0 0 0
The_System|mm_interconnect_0|cmd_mux|arb 7 0 1 0 3 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|cmd_mux 381 0 0 0 129 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|cmd_demux_002 132 4 3 4 253 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|cmd_demux_001 132 4 3 4 253 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|cmd_demux 132 4 3 4 253 4 4 4 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_ff800000_expanded_master_limiter 256 1 1 1 256 1 1 1 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_ff600000_expanded_master_limiter 256 1 1 1 256 1 1 1 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_00000000_expanded_master_limiter 256 1 1 1 256 1 1 1 0 0 0 0 0
The_System|mm_interconnect_0|router_004|the_default_decode 0 3 0 3 3 3 3 3 0 0 0 0 0
The_System|mm_interconnect_0|router_004 162 0 2 0 163 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|router_003|the_default_decode 0 3 0 3 3 3 3 3 0 0 0 0 0
The_System|mm_interconnect_0|router_003 162 0 2 0 163 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|router_002|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
The_System|mm_interconnect_0|router_002 126 0 4 0 127 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|router_001|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
The_System|mm_interconnect_0|router_001 126 0 4 0 127 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|router|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
The_System|mm_interconnect_0|router 126 0 4 0 127 0 0 0 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_agent|read_rsp_fifo 202 41 0 41 159 41 41 41 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_agent|write_rsp_fifo 202 41 0 41 159 41 41 41 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_agent|read_burst_uncompressor 58 1 0 1 56 1 1 1 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_agent|check_and_align_address_to_size 46 9 2 9 35 9 9 9 0 0 0 0 0
The_System|mm_interconnect_0|arm_a9_hps_f2h_axi_slave_agent 418 30 25 30 532 30 30 30 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_ff800000_expanded_master_agent 204 49 91 49 158 49 49 49 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_ff600000_expanded_master_agent 204 49 91 49 158 49 49 49 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_00000000_expanded_master_agent 204 49 91 49 158 49 49 49 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_ff800000_expanded_master_translator 116 11 2 11 109 11 11 11 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_ff600000_expanded_master_translator 116 11 2 11 109 11 11 11 0 0 0 0 0
The_System|mm_interconnect_0|f2h_mem_window_00000000_expanded_master_translator 116 11 2 11 109 11 11 11 0 0 0 0 0
The_System|mm_interconnect_0 306 0 0 0 314 0 0 0 0 0 0 0 0
The_System|vga_subsystem|rst_controller_001|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
The_System|vga_subsystem|rst_controller_001|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|rst_controller_001 33 31 0 31 1 31 31 31 0 0 0 0 0
The_System|vga_subsystem|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
The_System|vga_subsystem|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|rst_controller 33 31 0 31 1 31 31 31 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_rgb_resampler 14 0 0 0 34 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrfull_eq_comp1_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrfull_eq_comp1_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rdempty_eq_comp_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rdempty_eq_comp_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rdempty_eq_comp1_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rdempty_eq_comp1_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|ws_dgrp|dffpipe9 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|ws_dgrp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|ws_bwp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|ws_brp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rs_dgwp|dffpipe6 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rs_dgwp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|fifo_ram 28 0 0 0 10 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrptr_g1p 2 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|rdptr_g1p 2 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|ws_dgrp_gray2bin 8 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated|wrptr_g_gray2bin 8 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo|Data_FIFO|auto_generated 14 0 0 0 18 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_fifo 16 0 2 0 12 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated|dpfifo|wr_ptr 3 0 0 0 7 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated|dpfifo|usedw_counter 4 0 0 0 7 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated|dpfifo|rd_ptr_msb 3 0 0 0 6 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated|dpfifo|three_comparison 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated|dpfifo|almost_full_comparer 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated|dpfifo|FIFOram 26 0 0 0 10 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated|dpfifo 14 0 0 0 19 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma|Image_Buffer|auto_generated 14 0 0 0 14 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pixel_dma 53 0 0 0 77 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pll|reset_from_locked 1 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pll|video_pll 2 0 0 0 4 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_pll 2 0 0 0 2 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrfull_eq_comp_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrfull_eq_comp1_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrfull_eq_comp1_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rdempty_eq_comp_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rdempty_eq_comp_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rdempty_eq_comp1_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rdempty_eq_comp1_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|ws_dgrp|dffpipe16 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|ws_dgrp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|ws_bwp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|ws_brp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rs_dgwp|dffpipe12 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rs_dgwp 9 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|fifo_ram 50 0 0 0 32 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrptr_g1p 2 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|rdptr_g1p 2 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|ws_dgrp_gray2bin 8 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated|wrptr_g_gray2bin 8 0 0 0 8 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo|Data_FIFO|auto_generated 36 0 0 0 40 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_dual_clock_fifo 38 0 2 0 34 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_controller|VGA_Timing 30 0 1 0 39 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_controller 35 0 7 0 30 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_char_buffer|Character_Rom|character_data_rom|auto_generated 15 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_char_buffer|Character_Rom 15 0 0 0 1 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_char_buffer|Char_Buffer_Memory|auto_generated 47 0 0 0 16 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_char_buffer 68 1 1 1 84 1 1 1 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender|alpha_blender|b_times_one_minus_alpha|auto_generated 18 0 0 0 18 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender|alpha_blender|g_times_one_minus_alpha|auto_generated 18 0 0 0 18 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender|alpha_blender|r_times_one_minus_alpha|auto_generated 18 0 0 0 18 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender|alpha_blender|b_times_alpha|auto_generated 18 0 0 0 18 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender|alpha_blender|g_times_alpha|auto_generated 18 0 0 0 18 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender|alpha_blender|r_times_alpha|auto_generated 18 0 0 0 18 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender|alpha_blender 70 0 7 0 30 0 0 0 0 0 0 0 0
The_System|vga_subsystem|vga_alpha_blender 79 0 3 0 35 0 0 0 0 0 0 0 0
The_System|vga_subsystem 119 0 0 0 136 0 0 0 0 0 0 0 0
The_System|system_pll|reset_from_locked 1 0 0 0 1 0 0 0 0 0 0 0 0
The_System|system_pll|sys_pll 2 0 0 0 3 0 0 0 0 0 0 0 0
The_System|system_pll 2 0 0 0 3 0 0 0 0 0 0 0 0
The_System|sysid 3 17 2 17 32 17 17 17 0 0 0 0 0
The_System|slider_switches 14 0 0 0 32 0 0 0 0 0 0 0 0
The_System|sdram|the_Computer_System_SDRAM_input_efifo_module 48 0 0 0 48 0 0 0 0 0 0 0 0
The_System|sdram 48 1 1 1 40 1 1 1 16 0 0 0 0
The_System|pushbuttons 42 0 28 0 33 0 0 0 0 0 0 0 0
The_System|pixel_dma_addr_translation 75 0 2 0 73 0 0 0 0 0 0 0 0
The_System|onchip_sram|the_altsyncram|auto_generated|mux5 259 0 0 0 32 0 0 0 0 0 0 0 0
The_System|onchip_sram|the_altsyncram|auto_generated|mux4 259 0 0 0 32 0 0 0 0 0 0 0 0
The_System|onchip_sram|the_altsyncram|auto_generated|decode3 4 0 0 0 8 0 0 0 0 0 0 0 0
The_System|onchip_sram|the_altsyncram|auto_generated|decode2 4 0 0 0 8 0 0 0 0 0 0 0 0
The_System|onchip_sram|the_altsyncram|auto_generated 110 0 0 0 64 0 0 0 0 0 0 0 0
The_System|onchip_sram 114 1 1 1 64 1 1 1 0 0 0 0 0
The_System|leds 38 22 22 22 42 22 22 22 0 0 0 0 0
The_System|hex3_hex0 38 16 16 16 48 16 16 16 0 0 0 0 0
The_System|f2h_mem_window_ff800000 111 77 0 77 71 77 77 77 0 0 0 0 0
The_System|f2h_mem_window_ff600000 111 77 0 77 71 77 77 77 0 0 0 0 0
The_System|f2h_mem_window_00000000 111 77 0 77 71 77 77 77 0 0 0 0 0
The_System|audio_subsystem|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
The_System|audio_subsystem|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
The_System|audio_subsystem|rst_controller 33 31 0 31 1 31 31 31 0 0 0 0 0
The_System|audio_subsystem|audio_pll|reset_from_locked 1 0 0 0 1 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio_pll|audio_pll 2 0 0 0 2 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio_pll 2 0 0 0 2 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr 3 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter 4 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb 3 0 0 0 6 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram 48 0 0 0 32 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO|Sync_FIFO|auto_generated 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Right_Channel_FIFO 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr 3 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter 4 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb 3 0 0 0 6 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram 48 0 0 0 32 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO|Sync_FIFO|auto_generated 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer|Audio_Out_Left_Channel_FIFO 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_Out_Serializer 72 0 1 0 17 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr 3 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter 4 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb 3 0 0 0 6 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram 48 0 0 0 32 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO|Sync_FIFO|auto_generated 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Right_Channel_FIFO 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr 3 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter 4 0 0 0 7 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb 3 0 0 0 6 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer 14 7 0 7 1 7 7 7 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram 48 0 0 0 32 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated|dpfifo 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO|Sync_FIFO|auto_generated 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_In_Left_Channel_FIFO 36 0 0 0 41 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer|Audio_Out_Bit_Counter 6 0 1 0 1 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Audio_In_Deserializer 10 0 0 0 80 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|DAC_Left_Right_Clock_Edges 3 0 1 0 2 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|ADC_Left_Right_Clock_Edges 3 0 1 0 2 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio|Bit_Clock_Edges 3 0 1 0 2 0 0 0 0 0 0 0 0
The_System|audio_subsystem|audio 43 0 0 0 34 0 0 0 0 0 0 0 0
The_System|audio_subsystem 45 0 0 0 35 0 0 0 0 0 0 0 0
The_System|av_config|Serial_Bus_Controller|Serial_Config_Clock_Generator 3 1 0 1 3 1 1 1 0 0 0 0 0
The_System|av_config|Serial_Bus_Controller 116 84 0 84 30 84 84 84 1 0 0 0 0
The_System|av_config|Auto_Init_OB_Devices_ROM|Auto_Init_Video_ROM 6 3 0 3 27 3 3 3 0 0 0 0 0
The_System|av_config|Auto_Init_OB_Devices_ROM|Auto_Init_Audio_ROM 6 12 0 12 27 12 12 12 0 0 0 0 0
The_System|av_config|Auto_Init_OB_Devices_ROM 6 0 0 0 27 0 0 0 0 0 0 0 0
The_System|av_config|AV_Config_Auto_Init 32 1 0 1 36 1 1 1 0 0 0 0 0
The_System|av_config 42 0 22 0 34 0 0 0 1 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|dll 2 0 0 0 7 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|oct 1 0 0 0 32 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|c0 228 173 8 173 280 173 173 173 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|seq 0 0 0 0 0 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator 1 0 0 0 2 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated 3 0 0 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad 7 1 0 1 1 1 1 1 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad 37 1 0 1 6 1 1 1 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad 19 1 0 1 3 1 1 1 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad 91 1 0 1 15 1 1 1 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[24].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[23].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads 118 0 5 0 27 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads 633 58 118 58 220 58 58 58 40 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc 10 0 1 0 4 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy 975 1 2 1 366 1 1 1 40 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0 878 545 0 545 130 545 545 545 40 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|pll 2 1 2 1 12 1 1 1 0 0 0 0 0
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst 1 0 0 0 31 0 0 0 40 0 0 0 0
The_System|arm_a9_hps|hps_io|border 0 0 0 0 0 0 0 0 0 0 0 0 0
The_System|arm_a9_hps|hps_io 12 0 0 0 46 0 0 0 70 0 0 0 0
The_System|arm_a9_hps|fpga_interfaces 507 0 0 0 529 0 0 0 0 0 0 0 0
The_System|arm_a9_hps 519 0 0 0 575 0 0 0 70 0 0 0 0
The_System 0 0 0 0 0 0 0 0 0 0 0 0 0
Digit3 0 0 0 0 0 0 0 0 0 0 0 0 0
Digit2 0 0 0 0 0 0 0 0 0 0 0 0 0
Digit1 0 0 0 0 0 0 0 0 0 0 0 0 0
Digit0 0 0 0 0 0 0 0 0 0 0 0 0 0