The Altera DE2 Development and Education Board provides an ideal vehicle for learning about digital logic, computer organization, and FPGAs. Featuring an Altera Cyclone II FPGA, the DE2 board offers state-of-the-art technology suitable for university and college laboratory use, a wide range of design projects, as well as sophisticated digital system development.

 

Nios II Web Server Demo

This page is being served from a web server running on a Nios II general-purpose processor.
The Nios II processor is running LWIP on the MicroC/OS-II RTOS. The web server uses the industry standard sockets interface to TCP/IP.
The file system is a single zip file created using WinZip.
You can get all of this and more in a Nios II Development Kit.


Want to replace this with your own custom web content? Follow these steps to do so:

1. Open the file "ro_zipfs.zip" in your Nios II IDE system library project that this web server was built with.
2. Add & remove your custom web content. For best results, always include "index.html" and "not_found.html" files in the root. Other files may follow a directory structure.
3. Save the .zip file with the additional files. Make sure that compression is OFF.
4. Re-compile your system library & re-program flash as described in the web-server example design readme.txt file.
5.

Keep content sensible in size -- your DE2 board has a limited amount of flash memory. Refer to the DE2 user manual for more information.

Note: Content you add must be of a known "type" to be served properly. HTML, GIF, and JPEG images are a few supported by this example application. For more advanced file types you'll need to modify the web-server example application!


** More Demo and Reference Design can be downloaded from http://de2.terasic.com

 

Supporting Supplier: Davicom