Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
cpu3|dpram0 |
44 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu3|alu0|m_10_8 |
36 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu3|alu0 |
41 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu3|stackm0 |
43 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu3|statef0 |
4 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
cpu3 |
75 |
38 |
0 |
38 |
72 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
cpu2|dpram0 |
44 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu2|alu0|m_10_8 |
36 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu2|alu0 |
41 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu2|stackm0 |
43 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu2|statef0 |
4 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
cpu2 |
75 |
38 |
0 |
38 |
72 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
cpu1|dpram0 |
44 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1|alu0|m_10_8 |
36 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1|alu0 |
41 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1|stackm0 |
43 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1|statef0 |
4 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
cpu1 |
75 |
38 |
0 |
38 |
72 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
cmap |
8 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1 |
36 |
6 |
0 |
6 |
74 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
p1 |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
r0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |