Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
cpu1|ram0 |
32 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1|alu0 |
41 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1|stack0 |
23 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1|state0 |
5 |
2 |
0 |
2 |
3 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
cpu1|ir0 |
22 |
1 |
0 |
1 |
18 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
cpu1|pc0 |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
cpu1 |
56 |
30 |
0 |
30 |
72 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
cmap |
8 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u1 |
36 |
6 |
0 |
6 |
74 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
p1 |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
r0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |