| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| m4k_block|altsyncram_component|auto_generated|mux2 |
83 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m4k_block|altsyncram_component|auto_generated|deep_decode |
8 |
1 |
0 |
1 |
76 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| m4k_block|altsyncram_component|auto_generated|decode3 |
8 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m4k_block|altsyncram_component|auto_generated |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m4k_block |
21 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| display2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| display1 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| display0 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dxdy |
6 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ball_position |
28 |
1 |
0 |
1 |
20 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| rgb_control |
312 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| match |
21 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| audio |
35 |
30 |
0 |
30 |
35 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| u8|comb_130|altsyncram_component|auto_generated |
32 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|comb_130 |
32 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|comb_96|altsyncram_component|auto_generated |
32 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|comb_96 |
32 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|comb_62|altsyncram_component|auto_generated |
32 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|comb_62 |
32 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8 |
33 |
0 |
0 |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u0 |
27 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| u7 |
18 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo2 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|read_fifo1 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo2 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|fifo_ram|altsyncram14 |
58 |
17 |
0 |
17 |
16 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|write_fifo1 |
21 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|data_path1 |
20 |
2 |
0 |
2 |
18 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u6|command1 |
35 |
0 |
2 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6|control1 |
30 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u6|sdram_pll1 |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6 |
266 |
224 |
0 |
224 |
55 |
224 |
224 |
224 |
16 |
0 |
0 |
0 |
0 |
| u5|u7 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u6 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u5 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u4 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u1 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u0 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5 |
32 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|altshift_taps_component|auto_generated|cntr1|cmpr5 |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|altshift_taps_component|auto_generated|cntr1 |
2 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|altshift_taps_component|auto_generated|altsyncram2 |
45 |
1 |
0 |
1 |
20 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|altshift_taps_component|auto_generated |
12 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0 |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4 |
35 |
0 |
20 |
0 |
31 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u3 |
16 |
0 |
0 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u2 |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u1 |
86 |
35 |
20 |
35 |
55 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |