Real-Time Arbitrage Trading System
Vidhula Iyer Pallavor
Arbitrage is a trading algorithm where the trader monitors the prices of an asset, usually stocks, across different markets to identify where its price is the lowest and highest. The stock is purchased at a low price and sold at a high price. But since markets tend to adjust prices quickly, speed is of utmost importance to make profits. Here I tried to leverage the speed and parallelization offered by Field Programmable Gate Arrays (FPGAs) to make an Arbitrage Trading system. The FPGA used in this system is the DE1 SoC by Altera/ Intel.
Fig1. Flowchart of Project Structure
DE1 SoC supports Fast Ethernet with the speed of 100Mbps. Ethernet was used to send the data packets to the HPS of the DE1-SoC board in the format-
"<stock_name>, <price_in_stock_exchange_ASE>,<price_in_stock_exchange_BSE>,<price_in_stock_exchange_CSE>"
Fig2. Data packets sent via Ethernet
The Hard Processor System (HPS) on the DE1-SoC manages Ethernet communication and visualization. It establishes the connection to the network to receive real-time stock market data, parsing incoming packets to extract the stock prices. This data is then transferred to the FPGA for processing.
The HPS handles dynamic data management using a circular buffer structure, ensuring efficient storage and retrieval of stock information. It maintains a continuous flow of incoming data while dynamically updating the buffer to keep only the latest relevant information.
Additionally, the HPS configures and controls the VGA display interface, setting up the necessary frame buffer memory. It sends stock visualization parameters, such as scaling factors and graph layouts, to the FPGA for real-time rendering.
The FPGA handles the main computation of the Arbitrage Trading System. The trading logic, implemented in Verilog, is designed to compare stock prices across three different markets and determine the optimal buy/sell actions to capitalize on arbitrage opportunities. This logic processes data inputs in real-time, leveraging the FPGA's ability to parallelize operations and minimize latency.
It takes stock price inputs from three markets (Market A, Market B, and Market C) and processes them to identify arbitrage opportunities. For every stock, the FPGA compares prices across the markets and outputs actions—Buy, Sell, or Hold—for each market. For instance, if Market A offers the stock at the lowest price and Market C has the highest, the FPGA sets the corresponding outputs to "Buy" for Market A and "Sell" for Market C. These decisions are made within a single clock cycle, ensuring responsiveness critical for financial applications.
Fig 3. Arbitrage trade algorithm on FPGA
The design accounts for multiple stocks by using arrays to store and update the last actions for each stock. This allows the system to manage trades for multiple stocks concurrently, highlighting the FPGA's inherent advantage in handling parallel processes.
The outputs of the FPGA are communicated back to the HPS, which then aggregates and visualizes the results on a VGA display. The tight integration between the FPGA and the HPS ensures seamless data flow and real-time execution of the trading algorithm.
The 640x480 Video Graphics Array (VGA) display was used to visualize the results real-time. I plotted a line graph showing the change in the trading firm’s assets with each purchase and the price movements of each stock exchange .
The HPS sends configuration details for the display, such as the resolution, color coding for different stocks or trends, and layout parameters, while the FPGA handles the rendering of these visuals.
Fig 4. VGA output
(In the plot to the right, the red line corresponds to ASE, green to BSE and blue to CSE)
The various units of the system were tested individually before being integrated into the arbitrage trade system.
The trade algorithm was tested on Modelsim with edge cases to identify if it was able to correctly identify the lowest and highest prices to determine the trade.
Test input:
initial begin
reset = 1; // Assert reset
#15 reset = 0; // Deassert reset after 15 time units
#10;
price_a_reg = 16'd100;
price_b_reg = 16'd200;
price_c_reg = 16'd400; // All different- Buy A, Sell C
#50;
price_a_reg = 16'd150; // 2 SEs have same price
price_b_reg = 16'd150;
price_c_reg = 16'd350; // Buy A, Sell C
#50;
price_a_reg = 16'd370; // All SEs have same price
price_b_reg = 16'd370;
price_c_reg = 16'd270; // Do nothing
#50;
$finish; // End simulation
end
Result of test:
# Buy A at price 100
# Sell C at price 400
# Buy A at price 150
# Sell C at price 350
The Ethernet transmission from the PC connected to the network and the DE1-SoC was verified.
The below transactions were fed to the system-
"AAPL,150,200,250",#Trade- profit = 100
"GOOG,120,150,220",#Trade- profit = 100
"MSFT,200,180,210",#Trade- profit = 30
"TSLA,130,190,240",#Trade- profit = 110
"AAPL,140,180,230",#Trade- profit = 90
"GOOG,150,170,210",#Trade- profit = 60
"MSFT,160,160,220",#Trade- profit = 60
"TSLA,140,140,140",#No trade
"AAPL,250,200,150",#Trade- profit = 100
"GOOG,220,150,120",#Trade- profit = 100
"MSFT,210,180,200",#Trade- profit = 30
"TSLA,190,130,240",#Trade- profit = 110
"AAPL,180,140,230",#Trade- profit = 90
"GOOG,170,150,210",#Trade- profit = 60
"MSFT,160,220,160",#Trade- profit = 60
"TSLA,100,100,100",#No trade
"AAPL,200,150,250",#Trade- profit = 100
"GOOG,150,120,220",#Trade- profit = 100
"MSFT,200,210,180",#Trade- profit = 30
"TSLA,240,190,130",#Trade- profit = 110
"AAPL,140,230,180",#Trade- profit = 90
"GOOG,150,210,170",#Trade- profit = 60
"MSFT,220,160,160",#Trade- profit = 60
"TSLA,40,40,40",#No trade
Expected output-
Asset = 1750 (Beginning balance = 100)
Actual output- 1750
In conclusion, this project demonstrates the successful implementation of a Real-Time Arbitrage Trading System leveraging the speed and parallelization capabilities of FPGAs. By using the DE1-SoC by Altera/Intel, we were able to design a system that efficiently monitors stock prices across multiple markets and makes real-time trading decisions based on arbitrage opportunities. However, there is some room for improvement.
I originally aimed to establish a direct Ethernet connection through the FPGA, bypassing the HPS (as outlined in Future Scope point 2). The proposed design involved using an RJ45 breakout board to interface with the FPGA's PIO pins, configuring the RX+ and RX- pins for communication. However, due to time constraints, I was unable to implement this. Despite this, the experience provided valuable insights into Ethernet communication and its integration with FPGA designs.
