// -------------------------------------------------------------------- // Low accuracy FP for DSP // {sign, exp, mantissa} // sign is zero if positive, // exp is 8 bit offset binary (e.g. 2**0 is 128 and 2**1 is 129 // mantissa is 9 bit fraction >=0.5 and <1.0 OR ZERO // -------------------------------------------------------------------- // // Bruce Land, August/Sept 2008, Cornell University, ECE5760 // // -------------------------------------------------------------------- //////////////////////////////////////////////////////////////////////// module DE2_TOP ( //////////////////// Clock Input //////////////////// CLOCK_27, // 27 MHz CLOCK_50, // 50 MHz EXT_CLOCK, // External Clock //////////////////// Push Button //////////////////// KEY, // Pushbutton[3:0] //////////////////// DPDT Switch //////////////////// SW, // Toggle Switch[17:0] //////////////////// 7-SEG Dispaly //////////////////// HEX0, // Seven Segment Digit 0 HEX1, // Seven Segment Digit 1 HEX2, // Seven Segment Digit 2 HEX3, // Seven Segment Digit 3 HEX4, // Seven Segment Digit 4 HEX5, // Seven Segment Digit 5 HEX6, // Seven Segment Digit 6 HEX7, // Seven Segment Digit 7 //////////////////////// LED //////////////////////// LEDG, // LED Green[8:0] LEDR, // LED Red[17:0] //////////////////////// UART //////////////////////// UART_TXD, // UART Transmitter UART_RXD, // UART Receiver //////////////////////// IRDA //////////////////////// IRDA_TXD, // IRDA Transmitter IRDA_RXD, // IRDA Receiver ///////////////////// SDRAM Interface //////////////// DRAM_DQ, // SDRAM Data bus 16 Bits DRAM_ADDR, // SDRAM Address bus 12 Bits DRAM_LDQM, // SDRAM Low-byte Data Mask DRAM_UDQM, // SDRAM High-byte Data Mask DRAM_WE_N, // SDRAM Write Enable DRAM_CAS_N, // SDRAM Column Address Strobe DRAM_RAS_N, // SDRAM Row Address Strobe DRAM_CS_N, // SDRAM Chip Select DRAM_BA_0, // SDRAM Bank Address 0 DRAM_BA_1, // SDRAM Bank Address 0 DRAM_CLK, // SDRAM Clock DRAM_CKE, // SDRAM Clock Enable //////////////////// Flash Interface //////////////// FL_DQ, // FLASH Data bus 8 Bits FL_ADDR, // FLASH Address bus 22 Bits FL_WE_N, // FLASH Write Enable FL_RST_N, // FLASH Reset FL_OE_N, // FLASH Output Enable FL_CE_N, // FLASH Chip Enable //////////////////// SRAM Interface //////////////// SRAM_DQ, // SRAM Data bus 16 Bits SRAM_ADDR, // SRAM Address bus 18 Bits SRAM_UB_N, // SRAM High-byte Data Mask SRAM_LB_N, // SRAM Low-byte Data Mask SRAM_WE_N, // SRAM Write Enable SRAM_CE_N, // SRAM Chip Enable SRAM_OE_N, // SRAM Output Enable //////////////////// ISP1362 Interface //////////////// OTG_DATA, // ISP1362 Data bus 16 Bits OTG_ADDR, // ISP1362 Address 2 Bits OTG_CS_N, // ISP1362 Chip Select OTG_RD_N, // ISP1362 Write OTG_WR_N, // ISP1362 Read OTG_RST_N, // ISP1362 Reset OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable OTG_INT0, // ISP1362 Interrupt 0 OTG_INT1, // ISP1362 Interrupt 1 OTG_DREQ0, // ISP1362 DMA Request 0 OTG_DREQ1, // ISP1362 DMA Request 1 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1 //////////////////// LCD Module 16X2 //////////////// LCD_ON, // LCD Power ON/OFF LCD_BLON, // LCD Back Light ON/OFF LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read LCD_EN, // LCD Enable LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data LCD_DATA, // LCD Data bus 8 bits //////////////////// SD_Card Interface //////////////// SD_DAT, // SD Card Data SD_DAT3, // SD Card Data 3 SD_CMD, // SD Card Command Signal SD_CLK, // SD Card Clock //////////////////// USB JTAG link //////////////////// TDI, // CPLD -> FPGA (data in) TCK, // CPLD -> FPGA (clk) TCS, // CPLD -> FPGA (CS) TDO, // FPGA -> CPLD (data out) //////////////////// I2C //////////////////////////// I2C_SDAT, // I2C Data I2C_SCLK, // I2C Clock //////////////////// PS2 //////////////////////////// PS2_DAT, // PS2 Data PS2_CLK, // PS2 Clock //////////////////// VGA //////////////////////////// VGA_CLK, // VGA Clock VGA_HS, // VGA H_SYNC VGA_VS, // VGA V_SYNC VGA_BLANK, // VGA BLANK VGA_SYNC, // VGA SYNC VGA_R, // VGA Red[9:0] VGA_G, // VGA Green[9:0] VGA_B, // VGA Blue[9:0] //////////// Ethernet Interface //////////////////////// ENET_DATA, // DM9000A DATA bus 16Bits ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data ENET_CS_N, // DM9000A Chip Select ENET_WR_N, // DM9000A Write ENET_RD_N, // DM9000A Read ENET_RST_N, // DM9000A Reset ENET_INT, // DM9000A Interrupt ENET_CLK, // DM9000A Clock 25 MHz //////////////// Audio CODEC //////////////////////// AUD_ADCLRCK, // Audio CODEC ADC LR Clock AUD_ADCDAT, // Audio CODEC ADC Data AUD_DACLRCK, // Audio CODEC DAC LR Clock AUD_DACDAT, // Audio CODEC DAC Data AUD_BCLK, // Audio CODEC Bit-Stream Clock AUD_XCK, // Audio CODEC Chip Clock //////////////// TV Decoder //////////////////////// TD_DATA, // TV Decoder Data bus 8 bits TD_HS, // TV Decoder H_SYNC TD_VS, // TV Decoder V_SYNC TD_RESET, // TV Decoder Reset //////////////////// GPIO //////////////////////////// GPIO_0, // GPIO Connection 0 GPIO_1 // GPIO Connection 1 ); //////////////////////// Clock Input //////////////////////// input CLOCK_27; // 27 MHz input CLOCK_50; // 50 MHz input EXT_CLOCK; // External Clock //////////////////////// Push Button //////////////////////// input [3:0] KEY; // Pushbutton[3:0] //////////////////////// DPDT Switch //////////////////////// input [17:0] SW; // Toggle Switch[17:0] //////////////////////// 7-SEG Dispaly //////////////////////// output [6:0] HEX0; // Seven Segment Digit 0 output [6:0] HEX1; // Seven Segment Digit 1 output [6:0] HEX2; // Seven Segment Digit 2 output [6:0] HEX3; // Seven Segment Digit 3 output [6:0] HEX4; // Seven Segment Digit 4 output [6:0] HEX5; // Seven Segment Digit 5 output [6:0] HEX6; // Seven Segment Digit 6 output [6:0] HEX7; // Seven Segment Digit 7 //////////////////////////// LED //////////////////////////// output [8:0] LEDG; // LED Green[8:0] output [17:0] LEDR; // LED Red[17:0] //////////////////////////// UART //////////////////////////// output UART_TXD; // UART Transmitter input UART_RXD; // UART Receiver //////////////////////////// IRDA //////////////////////////// output IRDA_TXD; // IRDA Transmitter input IRDA_RXD; // IRDA Receiver /////////////////////// SDRAM Interface //////////////////////// inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits output DRAM_LDQM; // SDRAM Low-byte Data Mask output DRAM_UDQM; // SDRAM High-byte Data Mask output DRAM_WE_N; // SDRAM Write Enable output DRAM_CAS_N; // SDRAM Column Address Strobe output DRAM_RAS_N; // SDRAM Row Address Strobe output DRAM_CS_N; // SDRAM Chip Select output DRAM_BA_0; // SDRAM Bank Address 0 output DRAM_BA_1; // SDRAM Bank Address 0 output DRAM_CLK; // SDRAM Clock output DRAM_CKE; // SDRAM Clock Enable //////////////////////// Flash Interface //////////////////////// inout [7:0] FL_DQ; // FLASH Data bus 8 Bits output [21:0] FL_ADDR; // FLASH Address bus 22 Bits output FL_WE_N; // FLASH Write Enable output FL_RST_N; // FLASH Reset output FL_OE_N; // FLASH Output Enable output FL_CE_N; // FLASH Chip Enable //////////////////////// SRAM Interface //////////////////////// inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits output SRAM_UB_N; // SRAM High-byte Data Mask output SRAM_LB_N; // SRAM Low-byte Data Mask output SRAM_WE_N; // SRAM Write Enable output SRAM_CE_N; // SRAM Chip Enable output SRAM_OE_N; // SRAM Output Enable //////////////////// ISP1362 Interface //////////////////////// inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits output OTG_CS_N; // ISP1362 Chip Select output OTG_RD_N; // ISP1362 Write output OTG_WR_N; // ISP1362 Read output OTG_RST_N; // ISP1362 Reset output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable input OTG_INT0; // ISP1362 Interrupt 0 input OTG_INT1; // ISP1362 Interrupt 1 input OTG_DREQ0; // ISP1362 DMA Request 0 input OTG_DREQ1; // ISP1362 DMA Request 1 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1 //////////////////// LCD Module 16X2 //////////////////////////// inout [7:0] LCD_DATA; // LCD Data bus 8 bits output LCD_ON; // LCD Power ON/OFF output LCD_BLON; // LCD Back Light ON/OFF output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read output LCD_EN; // LCD Enable output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data //////////////////// SD Card Interface //////////////////////// inout SD_DAT; // SD Card Data inout SD_DAT3; // SD Card Data 3 inout SD_CMD; // SD Card Command Signal output SD_CLK; // SD Card Clock //////////////////////// I2C //////////////////////////////// inout I2C_SDAT; // I2C Data output I2C_SCLK; // I2C Clock //////////////////////// PS2 //////////////////////////////// input PS2_DAT; // PS2 Data input PS2_CLK; // PS2 Clock //////////////////// USB JTAG link //////////////////////////// input TDI; // CPLD -> FPGA (data in) input TCK; // CPLD -> FPGA (clk) input TCS; // CPLD -> FPGA (CS) output TDO; // FPGA -> CPLD (data out) //////////////////////// VGA //////////////////////////// output VGA_CLK; // VGA Clock output VGA_HS; // VGA H_SYNC output VGA_VS; // VGA V_SYNC output VGA_BLANK; // VGA BLANK output VGA_SYNC; // VGA SYNC output [9:0] VGA_R; // VGA Red[9:0] output [9:0] VGA_G; // VGA Green[9:0] output [9:0] VGA_B; // VGA Blue[9:0] //////////////// Ethernet Interface //////////////////////////// inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data output ENET_CS_N; // DM9000A Chip Select output ENET_WR_N; // DM9000A Write output ENET_RD_N; // DM9000A Read output ENET_RST_N; // DM9000A Reset input ENET_INT; // DM9000A Interrupt output ENET_CLK; // DM9000A Clock 25 MHz //////////////////// Audio CODEC //////////////////////////// inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock input AUD_ADCDAT; // Audio CODEC ADC Data inout AUD_DACLRCK; // Audio CODEC DAC LR Clock output AUD_DACDAT; // Audio CODEC DAC Data inout AUD_BCLK; // Audio CODEC Bit-Stream Clock output AUD_XCK; // Audio CODEC Chip Clock //////////////////// TV Devoder //////////////////////////// input [7:0] TD_DATA; // TV Decoder Data bus 8 bits input TD_HS; // TV Decoder H_SYNC input TD_VS; // TV Decoder V_SYNC output TD_RESET; // TV Decoder Reset //////////////////////// GPIO //////////////////////////////// inout [35:0] GPIO_0; // GPIO Connection 0 inout [35:0] GPIO_1; // GPIO Connection 1 assign LCD_ON = 1'b0; assign LCD_BLON = 1'b0; // All inout port turn to tri-state assign DRAM_DQ = 16'hzzzz; assign FL_DQ = 8'hzz; assign SRAM_DQ = 16'hzzzz; assign OTG_DATA = 16'hzzzz; assign LCD_DATA = 8'hzz; assign SD_DAT = 1'bz; assign I2C_SDAT = 1'bz; assign ENET_DATA = 16'hzzzz; assign AUD_ADCLRCK = 1'bz; assign AUD_DACLRCK = 1'bz; assign AUD_BCLK = 1'bz; assign GPIO_0 = 36'hzzzzzzzzz; assign GPIO_1 = 36'hzzzzzzzzz; ////////////////////// wire [17:0] f1, f2, fout, mfout, afout ; wire [9:0] int_out ; // set f2 to lower 10 switches // set f1 to upper 8 switches // and convert both integers to floats int2fp i2f1(f2, SW[9:0], 0) ; int2fp i2f2(f1, SW[17:10], 0) ; fp2int f2i1(int_out, fout, 0); // get fout for multiply and add fpmult mult1(mfout, f1, f2) ; fpadd add1(afout, f1, f2) ; assign fout = (~KEY[3])? afout : mfout ; //~KEY[3] /* // fout mantissa HexDigit H0(HEX0,fout[0]); HexDigit H1(HEX1,fout[4:1]); HexDigit H2(HEX2,fout[8:5]); HexDigit H3(HEX3,4'b0); // turn it off // fout exp HexDigit H4(HEX4,fout[12:9]); HexDigit H5(HEX5,fout[16:13]); // fout sign HexDigit H6(HEX6,fout[17]); HexDigit H7(HEX7,4'b0); // turn it off */ HexDigit H0(HEX0,int_out[3:0]); HexDigit H1(HEX1,int_out[7:4]); HexDigit H2(HEX2,int_out[9:8]); HexDigit H3(HEX3,4'b0); // turn it off endmodule ////////////////////////////////////////////// // Decode one hex digit for LED 7-seg display ////////////////////////////////////////////////// module HexDigit(segs, num); input [3:0] num ; //the hex digit to be displayed output [6:0] segs ; //actual LED segments reg [6:0] segs ; always @ (num) begin case (num) 4'h0: segs = 7'b1000000; 4'h1: segs = 7'b1111001; 4'h2: segs = 7'b0100100; 4'h3: segs = 7'b0110000; 4'h4: segs = 7'b0011001; 4'h5: segs = 7'b0010010; 4'h6: segs = 7'b0000010; 4'h7: segs = 7'b1111000; 4'h8: segs = 7'b0000000; 4'h9: segs = 7'b0010000; 4'ha: segs = 7'b0001000; 4'hb: segs = 7'b0000011; 4'hc: segs = 7'b1000110; 4'hd: segs = 7'b0100001; 4'he: segs = 7'b0000110; 4'hf: segs = 7'b0001110; default segs = 7'b1111111; endcase end endmodule ////////////////////////////////////////////////////////// // floating point multiply // -- sign bit -- 8-bit exponent -- 9-bit mantissa // Similar to fp_mult from altera // NO denorms, no flags, no NAN, no infinity, no rounding! ////////////////////////////////////////////////////////// // f1 = {s1, e1, m1), f2 = {s2, e2, m2) // If either is zero (zero MSB of mantissa) then output is zero // If e1+e2<129 the result is zero (underflow) /////////////////////////////////////////////////////////// module fpmult (fout, f1, f2); input [17:0] f1, f2 ; output [17:0] fout ; reg [17:0] fout ; reg sout ; reg [8:0] mout ; reg [8:0] eout ; // 9-bits for overflow wire s1, s2; wire [8:0] m1, m2 ; wire [8:0] e1, e2 ; // extend to 9 bits to avoid overflow wire [17:0] mult_out ; // raw multiplier output // parse f1 assign s1 = f1[17]; // sign assign e1 = {1'b0, f1[16:9]}; // exponent assign m1 = f1[8:0] ; // mantissa // parse f2 assign s2 = f2[17]; assign e2 = {1'b0, f2[16:9]}; assign m2 = f2[8:0] ; // build output unsigned_mult mm(mult_out, m1, m2); always @(*) begin if ((f1[8]==0) || (f2[8]==0) || (e1+e2<9'h81)) fout = 18'h0 ; else // both inputs are not zero and no exponent underflow begin sout = s1 ^ s2 ; if (mult_out[17]==1) begin // MSB of product==1 implies normalized -- result >=0.5 eout = e1+e2-9'h80; mout = mult_out[17:9] ; end else // MSB of product==0 implies result <0.5 begin eout = e1+e2-9'h81; mout = mult_out[16:8] ; end fout = {sout, eout[7:0], mout} ; end // nonzero mult logic end // always @(*) endmodule /////////////////////////////////////// // low level integer multiply // From Altera HDL style manual /////////////////////////////////////// module unsigned_mult (out, a, b); output [17:0] out; input [8:0] a; input [8:0] b; assign out = a * b; endmodule ///////////////////////////////////////////////////////////////////////////// // floating point Add // -- sign bit -- 8-bit exponent -- 9-bit mantissa // NO denorms, no flags, no NAN, no infinity, no rounding! ///////////////////////////////////////////////////////////////////////////// // f1 = {s1, e1, m1), f2 = {s2, e2, m2) // If either input is zero (zero MSB of mantissa) then output is the remaining input. // If either input is <(other input)/2**9 then output is the remaining input. // Sign of the output is the sign of the greater magnitude input // Add the two inputs if their signs are the same. // Subtract the two inputs (bigger-smaller) if their signs are different ////////////////////////////////////////////////////////////////////////////// module fpadd (fout, f1, f2); input [17:0] f1, f2 ; output [17:0] fout ; reg [17:0] fout ; reg sout ; reg [8:0] mout ; reg [7:0] eout ; reg [9:0] shift_small, denorm_mout ; //9th bit is overflow bit wire s1, s2 ; // input signs reg sb, ss ; // signs of bigger and smaller wire [8:0] m1, m2 ; // input mantissas reg [8:0] mb, ms ; // mantissas of bigger and smaller wire [7:0] e1, e2 ; // input exp wire [7:0] ediff ; // exponent difference reg [7:0] eb, es ; // exp of bigger and smaller reg [7:0] num_zeros ; // high order zeros in the difference calc // parse f1 assign s1 = f1[17]; // sign assign e1 = f1[16:9]; // exponent assign m1 = f1[8:0] ; // mantissa // parse f2 assign s2 = f2[17]; assign e2 = f2[16:9]; assign m2 = f2[8:0] ; // find biggest magnitude always @(*) begin if (e1>e2) // f1 is bigger begin sb = s1 ; // the bigger number (absolute value) eb = e1 ; mb = m1 ; ss = s2 ; // the smaller number es = e2 ; ms = m2 ; end else if (e2>e1) //f2 is bigger begin sb = s2 ; // the bigger number (absolute value) eb = e2 ; mb = m2 ; ss = s1 ; // the smaller number es = e1 ; ms = m1 ; end else // e1==e2, so need to look at mantissa to determine bigger/smaller begin if (m1>m2) // f1 is bigger begin sb = s1 ; // the bigger number (absolute value) eb = e1 ; mb = m1 ; ss = s2 ; // the smaller number es = e2 ; ms = m2 ; end else // f2 is bigger or same size begin sb = s2 ; // the bigger number (absolute value) eb = e2 ; mb = m2 ; ss = s1 ; // the smaller number es = e1 ; ms = m1 ; end end end //found the bigger number // do the actual add: // -- equalize exponents // -- add/sub // -- normalize assign ediff = eb - es ; // the actual difference in exponents always @(*) begin if ((ms[8]==0) && (mb[8]==0)) fout = 18'h0 ; // both inputs are zero else if ((ms[8]==0) || ediff>8) fout = {sb,eb,mb} ; // smaller is too small to matter else // shift/add/normalize begin sout = sb ; // now shift but save the low order bits by extending the registers // need a high order bit for 1.0> ediff ; // same signs means add -- different means subtract if (sb==ss) //do the add begin denorm_mout = {1'b0, mb} + shift_small ; // normalize -- // when adding result has to be 0.5> (8'h89 - e_in - scale_in) ; assign int_out = {sign, sign? (~abs_int)+1 : abs_int} ; endmodule /////////////////////////////////////////////////////////////////////////////