EE 576: Laboratory 2

Implement your ECE475 cpu.

Introduction.

In this assignment you will implement a RISC cpu. You can use any reasonable RISC ISA and datapath you want. You can start from scratch, use your EC475 design, go to opencores.com or fpgacpu.com, or any of many course sites. You can use the Kraken design on my DE2 page as an example, but you cannot use it directly for this lab. You cannot use the NiosII design software. You need to code it yourself inVerilog.

Procedures:

1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the evaluation board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.
3. The default top level module for the DE2 defines all of the logical i/o signals.
4. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
5. The 7-segment displays can be run with a module shown near the end of a Verilog design from the DE2 page.
6. The Kraken example on the DE2 page shows how to instantiate RAM on the FPGA so that M4K RAM blocks are used.
7. The Altera HDL style manual page 6-23 shows how to infer ROM.

You may want to use the QuartusII SignalTap tool to verify your design. Here are the steps that seem to be necssary to get SignalTap working.

1. Choose menu Tools>SignalTap
2. In the main SignalTap window, click Hardware Setup... (in the upper rigtht corner)
   and in the dialog box choose the hardware (USB-Blaster)
3. Choose menu Edit>AddNodes...
   1. Choose the appropriate Filter to simplify the list of nodes, the press List
   2. Highlight nodes and move to right-hand list using > button
   3. Click OK to get back to main SignalTap window
4. In the main SignalTap window, click the Clock ... button and choose the clock signal as in AddNodes
5. In the node panel of the main window, set up trigger conditions.
6. Compile and then load the design onto the FPGA
7. In the main SignalTap window, toggle the Data/Setup button
8. Choose menu Processing >Run Analysis

• You will design the system in Verilog and compile it to the FPGA using QuartusII. Don't use schematic entry or VHDL. The Verilog code should be written at the level of registers, multiplexers, and ALU, so that if you have a data path diagram, there is a direct relationship between buses you have drawn and wires defined in the Verilog.
• You will implement a RISC cpu, then run assembly code on it.
• The cpu must be compute-universal.
• Minimally the asm code must contain nested loops and execute the following pseudocode:
  

   A: load immediate a register Rx with the constant 1
      load immediate a register Ry with the constant 4
   B: subtract Ry-Rx and store in Ry
      if Ry is not zero, branch to B
      load a RAM location, M, into Rz
      add 1 to Rz
      store Rz back to M
      unconditional branch to A 

• Your implementation needs to have enough output to the LEDs and/or 7-seg displays that you can determine the state of the machine. Perhaps putting the program counters, data bus, and memory address bus on the 7-seg displays would be sufficient.
• You can use FPGA on-chip memory or SRAM. You can use FPGA ROM or RAM for the assembler code. If you use RAM, you will need a method to load the program into memory.
• You should use KEY0 as the cpu reset and KEY3 as the cpu clock for single-step testing.
  

Be prepared to demo your design to your TA in lab.

Your written lab report should include:

• An RTL (register transfer level) data path of your design.
• A timing diagram for the interaction of memory and the cpu
• A heavily commented listing of your Verilog design.