EE 576: Laboratory 4

NiosII with microC/OS audio generator.


In this assignment you will implement a video interface to the NiosII processor, including lines and text, then use it to animate a ball dropping. You will use the SOPC builder to construct a NiosII processor, QuartusII to add an audio interface, and the NiosII IDE to write a GCC/microC/OS program to control an audio generator.


  1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
  2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the evaluation board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.
  3. The default top level module for the DE2 defines all of the logical i/o signals.
  4. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
  5. You will need to read the Audio Codec datasheet. See also example 4 on the DE2 hardware examples page.


Be prepared to demo your design to your TA in lab.

Your written lab report should include:

Copyright Cornell University July 2006