EE 576: Laboratory 0

Introduction to the hardware and software.

Introduction.

In this assignment you will build a circuit which reads some switches and produces a direct digital synthesis (DDS) sine wave.

Procedures:

1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.
3. The default top level module for the DE2 defines all of the logical i/o signals from the FPGA.
4. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
5. Read the Altera tutorial on using Verilog with QuartusII.
6. You may want to use the QuartusII SignalTap tool to verify your design. Here are the steps that seem to be necssary to get SignalTap working. For more information, read the Altera tutorial on using SignalTap, an on chip logic analyzer.
   1. Choose menu Tools>SignalTap
   2. In the main SignalTap window, click Hardware Setup... (in the upper rigtht corner)
      and in the dialog box choose the hardware (USB-Blaster)
   3. Choose menu Edit>AddNodes...
      1. Choose the appropriate Filter to simplify the list of nodes, the press List
      2. Highlight nodes and move to right-hand list using > button
      3. Click OK to get back to main SignalTap window
   4. In the main SignalTap window, click the Clock ... button and choose the clock signal as in AddNodes
   5. In the node panel of the main window, set up trigger conditions.
   6. Compile and then load the design onto the FPGA
   7. In the main SignalTap window, toggle the Data/Setup button
   8. Choose menu Processing >Run Analysis
7. The VGA output can operate as a 50 MHz D/A converter if you set the vga_blanking and vga_sync i/o signals high. Output the sine wave through the VGA red channel. The connector pinout is on the DE2 schematic.
8. You will need to generate a table containing 10-bit approxmations of a sine wave. You can precompute them and build the Verilog table in matlab using the following program, if you need 256 samples/cycle.

   %generate a sine table for Verilog ROM 
   x = 1:256;
   % Sin : scale to 10-bits and offset 9-bits
   y = fix(512 + 511*sin(2*pi*(x-1)/256)); 
   for i=x
       fprintf('\t\t\t8''h%02x: sine = 10''h%03x ;\n', x(i)-1 ,y(i))    
   end

9. When you come to lab, you should have a clean draft of the Verilog code required for the assignment.

• You will design the system in Verilog and compile it to the FPGA using QuartusII. Don't use schematic entry or VHDL.
• Build a circuit to produce a DDS sine wave at 50 MHz sample rate then output it through the red channel of the VGA connector.
• You should be able to enter the desired frequency in Hz using SW[17:0] and KEY3. When pressed, KEY3 will multiply the frequency by 16. As an example, setting only SW7 to the up position, and releasing KEY3, should produce 128 Hz. Setting only SW7 to the up position, and pressing KEY3, should produce 128*16=2048 Hz.
• Your implementation should have at least 32 sine samples/cycle at low frequencies.
• Do not build a general purpose CPU for this lab.

Be prepared to demo your design to your TA in lab and verify that the frequency is correct to the accuracy of the scope.

Your written lab report should include:

• An RTL (register transfer level) block diagran of your design.
• Other design aspects of the assignment.
• Why does the amplitude of the sine wave drop off at high frequencies (say above 1 MHz)?
• A heavily commented listing of your Verilog design.