EE 576: Laboratory 1
1-dimensional Cellular Automaton (CA).
In this assignment you will build a circuit which runs a state machine to compute and display a binary, nearest-neighbor, one-dimensional CA on a VGA monitor. The DE2 switches will be used to enter the rule number. An applet shows a display similar to what you should program. The rule number in the applet is entered by clicking boxes along the right edge of the interactive region.
- You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
- Make sure the Altera DE2 board is connected to power and to the PC as specified
in the evaluation board description. Turn on the power supply with the red switch
on the board. Make sure the toggle switch on the left edge of the board marked (
Run/Prog) is in the
Run position and leave it there at all times.
The FPGA will program in the
Run position. Putting the switch in the
Prog position writes your design to flash memory, which you do not want to do.
- You will probably want to look through the VGA examples on the DE2 hardware examples page to see one way of designing a memory state machine. Notice that you need to set up the address one cycle (at 27 MHz) before you read the data. The 61LV25616 SRAM memory data sheet suggest that it requires <20 nS to set up.
- The default top level module for the DE2 defines all of the logical i/o signals.
- You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item
Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
- You may want to use the QuartusII SignalTap tool to verify your design. Here are the steps that seem to be necssary to get SignalTap working. For more information, read the Altera tutorial on using SignalTap, an on chip logic analyzer.
- Choose menu
- In the main SignalTap window, click
Hardware Setup... (in the upper rigtht corner)
and in the dialog box choose the hardware (USB-Blaster)
- Choose menu
- Choose the appropriate
Filter to simplify the list of nodes, the press
- Highlight nodes and move to right-hand list using
OK to get back to main SignalTap window
- In the main SignalTap window, click the
Clock ... button and choose the clock signal as in AddNodes
- In the node panel of the main window, set up trigger conditions.
- Compile and then load the design onto the FPGA
- In the main SignalTap window, toggle the
- Choose menu
Processing >Run Analysis
- You will design the system in Verilog and compile it to the FPGA using QuartusII. Don't use schematic entry or VHDL.
- KEY0 will reset the state machine. The state machine will run at VGA clock rate.
- The VGA resolution must be at least 320x240.
- The initial state of the CA should be shown at the top of the VGA screen, each succeeding state should be shown on the next video line below.
- When the screen fills, the CA should stop until KEY3 is pressed, then exactly one more screen should be filled as if time is proceeding. In ohter words, the bottom line of the first screen should be copied to the top line of the second screen, and used as the initial condition.
- There should be no flickering, tearing, or other video artifacts caused by your state machine.
- The initial state will be exactly one cell at the center, top of the screen, or a random binary vector across the top of the screen. The initial state (seed or random) will be entered using SW17 and cannot be changed except at reset.
- The CA rule will be entered in binary on SW[7:0] and cannot be changed except at reset.
- Do not build a general purpose CPU for this lab.
Be prepared to demo your design to your TA in lab.
Your written lab report should include:
- An RTL (register transfer level) block diagran of your design.
- A state-transition diagram for the main CA update state machine.
- A photograph of the VGA screen showing the evolution of an interesting CA.
- A heavily commented listing of your Verilog design.
Copyright Cornell University July 2006