EE 576: Laboratory 3

NiosII with μC/OS audio generator.

Introduction.

In this assignment you will implement a audio interface to the NiosII processor. You will use the SOPC builder to construct a NiosII processor, QuartusII to add an audio interface, and the NiosII IDE to write a GCC/microC/OS program to control an audio generator.

Procedures:

1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the evaluation board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.
3. The default top level module for the DE2 defines all of the logical i/o signals.
4. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
5. You will need to read the Audio Codec datasheet. See also example 4 on the DE2 hardware examples page.

--Setting up a demo μC/OS project in QuartusII and the NiosII IDE:

1. Download the top-level module TestBigNios.v from the μC/OS page, example #1.
2. Copy the file sdram_pll.v and sdram_pll_bb.v from one of the zipped SDRAM examples, or generate a new PLL module as described in the SDRAM tutorial. If you find that memory cannot be loaded in step 14 below, then run the Megawizard Plugin Manager in the Tools... menu, choose edit, choose the sdram_pll.v file, then click through to the Finish, taking all the default options. This will regenerate any missing files.
3. Start quartusII
   1. choose menu File/ New project wizard
   2. change working dir to Z:\ece576\OStest (or whatever you choose, BUT with no spaces in the path)
   3. set top level design entity to TestBigNios
   4. click next
   5. click add all in design file dialog
   6. click next
   7. click finish
4. Back in the main QuartusII interface, open TestBigNios.v
5. Open SOPC builder:
   1. set system name to bigNios
   2. add standard NiosII (S)
   3. add (in this order, and with these names)
      1. sdram (settings 16-1-4-12-8)
      2. lcd
      3. jtag_uart
      4. Out0 (32-bit output port)
      5. Out1 (32-bit output port)
      6. In0 (32-bit input port)
      7. In1_8bit (8-bit input port)
      8. timer_0
   4. Generate the system
   5. Close SOPC builder (every time you open SOPC builder, the NiosII IDE has to rebuild syslib)
6. Back in the main QuartusII interface:
   1. Import the pin assignments file
   2. Make sure that the order of parameters generated by SOPC builder matches the order in the top-level module.
   3. Synthesize the Verilog in QuartusII
   4. Download the .sof file to the FPGA
7. When using the IDE there must be no space characters in the path you choose to your workspace!
8. Start the IDE
9. Specify a workspace. When you designed the cpu and top-level module, the design was stored in a folder. In the Workspace selection dialog box, browse for that folder, then add the string \software to the folder path. This new folder will be used to store all of the software projects associated with the specific cpu you built in the SOPC. After you press OK, you may need to click on the workbench icon to do anything useful.
10. Create a new software project. Select File>New>project. A series of dialog boxes will open.
    1. Choose C/C++ application, then click Next.
    2. Give the project a name, specify the ptf file from SOPC builder, use the default location, and specify a blank project.
       Then click Next.
    3. Select creat new system library then click finish.
11. Back in the main IDE window, right-click on the syslib entry in the C/C++ Projects pane, then select Properties.
    1. In the dialog box, select system library on the left.
    2. Associate the desired device with stdout, stdin, and stderr. These will usually default to the JTAG UART.
    3. From the pulldown menu, select microC/OS. Note that the web-version of the IDE does not support the operating system.
    4. Select the memory location, usually defaults to SDRAM.
    5. Make sure that the check box options are appropriate. Unselect the simulation only box.
    6. Click OK to proceed.
12. Back in the main IDE window, right-click on the syslib entry in the C/C++ Projects pane, then select Build Project.
    Wait for it to finish.
13. Create a newC file using File>New>file then and paste the contents of the demo program test1_mucosII.c into the new file. In the Nios II C/C++ Project pane, the project (not the syslib) should be highlighted before creating the new c file.
14. In Run... menu item be sure that the download option points to the actual project (not the syslib project). In the Run... dialog double-click the NiosII hardware option to find the USB-blaster device and download to the software to the NiosII
15. After the program loads, you should see scrolling text in the IDE console area

Another example, the third project ( μC/OS with ISR) on the μC/OS page is zipped here.

• You will design a cpu system, plus timers, UARTs and parallel interfaces in SOPC, then use Verilog to add the audio codec hardware interface. Don't use schematic entry or VHDL.
• You will use microC/OS to construct three tasks to:
  • Handle the JTAG-UART and set parameters from the human user using the NiosII IDE console area.
  • Display the waveform type and frequency on the LCD.
  • Communicate with the Audio Codec and synthesis hardware to produce the appropriate waveform.
• The audio generator should take a serial command to produce sine, square, triangle, white noise, or ( Karplus-Strong string--optional )
• Sine, square, or triangle waveforms should be produced by hardware (not in a cpu) Direct Digital Synthesis.
• The Karplus-Strong string sound should be produced in hardware. The string pluck should occur when a button is pushed.
• The audio generator should take a serial command to set the frequency if the wavefrom is sine, square, triangle, or string. The freqeucy should be settable to within 1 Hz for sine, square, triangle over a range of 1 Hz to 10 kHz. The string sound should be settable to within 1% over a range of fundamental of 50 Hz to 500 Hz..
• The audio generator should take a serial command to set the cutoff frequency of the white noise with a normalized frequency range of .05 to 0.5.
• White noise should be produced by using a hardware (not in a cpu) xor-feedback shift register or Linear Congruential Generator followed by a first order hardware digital low pass filter.

Be prepared to demo your design to your TA in lab.

Your written lab report should include:

• A explaination of the audio codec commands
• How you implemented the random number, DDS, and Karplus-Strong circuits.
• A heavily commented listing of your Verilog design and GCC with microC/OS code.