TimeQuest and the
Synopsis Design Constraint (sdc) File
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The TimeQuest timing analyser is Quartus Prime's timing verification tool.
TimeQuest requires information about connections and devices from Synopsis Design Constraint (sdc) file.
Chapter 6 and 7 in Quartus Prime Standard Edition Handbook Volume 3: Verification explains the types of analysis that TimeQuest runs.
The SDC and TimeQuest API Reference Manual has the full file syntax for a sdc file.
This A STANDARDIZED PROCEDURE FOR CLOSING TIMING ON OpenHPSDR FPGA FIRMWARE DESIGNS seems good. (another version).
Shows how to set up a minimal sdc file.

Examples of sdc files for the DE1-SoC.
Example from UofW, Another example, audio example, video, and Altera

Small example

For the example project DE1-SoC_v.5.0.1_HWrevF_SystemCD\Demonstrations\FPGA\my_first_fpga
which is a simple counter the sdc file is
create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
derive_pll_clocks
derive_clock_uncertainty

which leaves the i/o ports unconstrained but passes all other timing. This seems to be about the minimum file.
Deleting this file and having TimeQuest build a new file by

  1. Run Analysis
  2. Run Fitter
  3. In Tools>TimeQuest>Tasks pane, following the steps below appears to
    write an sdc file which includes clocks and PLLs.
    1. Right-click Create Timing Netlist and click start
    2. Right-click Read sdc file and click start
    3. Right-click Update Timing Netlist and click start
    4. Right-click Write sdc File and click start

This new sdc file contains more specific information about the clocks, and a bunch of unpopulated header suggestions.

Nios system

The example project DE1-SoC_v.5.0.1_HWrevF_SystemCD\Demonstrations\FPGA\\DE1_SoC_SDRAM_Nios_Test
ships with a simple sdc file, again defining the clocks. TimeQuest analysis fails Multicorner timing analysis using this sdc file.
Performing the steps above for TimeQuest gives a new sdc file. After substituting the new file (Assignments>Settings>TimeQuest) for the old, Recompiling shows that TimeQuest now passes everything, except for the unconstrained i/o paths. Generating the sdc file in TimeQuest appears to pick up the specific PLL settings and Quartus settings.

 


From Altera:
See also Timing Constraints

TimeQuest Example: Basic SDC Example

set_input_delay -clock clk -max 3 [all_inputs]

set_input_delay -clock clk -min 2 [all_inputs]The Synopsys Design Constraint (SDC) format provides a simple and easy method to constrain the simplest to the most complex designs. The following example provides the simplest SDC file content that constrains all clock (ports and pins), input I/O paths, and output I/O paths for a design. You can use the SDC file below as a template for any design. However, each design should contain a customized SDC file that individually constrains all clocks, input ports, and output ports.

# Constrain clock port clk with a 10-ns requirement

create_clock -period 10 [get_ports clk]

# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
# This command can be safely left in the SDC even if no PLLs exist in the design

derive_pll_clocks

# Constrain the input I/O path

set_input_delay -clock clk -max 3 [all_inputs]
set_input_delay -clock clk -min 2 [all_inputs]

# Constrain the output I/O path

set_output_delay -clock clk -max 3 [all_inputs]
set_output_delay -clock clk -min 2 [all_inputs]

 


Using TimeQuest Timing Analyzer (Quartus Prime)

Quartus Prime Standard Edition Handbook Volume 3: Verification Chapters 6 and 7

Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis