Stereoscopic Depth on an FPGA via OpenCL

By Ahmed Kamel and Aashish Agarwal


One of the greatest benefits of using a field programmable gate array (FPGA) is the ability
to do computationally heavy algorithms in an energy efficient environment and with relatively high
performance. The FPGA allows for the exploitation of highlevel synthesis tools such as OpenCL via the ARM cores
that it has available. For the proposed project, slightly horizontally offset image pairs
are taken in from a camera that has a stereoscopic lens. These images are then run through two
computationally heavy algorithms: bilateral filtering and segment based depth mapping. The bilateral
filter preserves the sharpness of the edges within the image while blurring out the excess noise within
the frame. The segment based depth mapping uses one image as a reference and pans through the other
to find the matching pixels and their position. This is done to construct a disparity map, which is used
to generate depth. One of the limitations in working with RTL is the developmental time due to the
programming environment. While programming at the register transfer level (RTL) is exceptionally
powerful in terms of utilizing the hardware correctly, it takes a large amount of time to develop. One
solution for this issue was to use a highlevel synthesis language, OpenCL. In previous years OpenCL
has been utilized GPU’s, but recently Altera has adapted this language for functionally on the FPGA.
One characteristic of OpenCL that made it ideal for this project was its ability to parallelize certain
tasks, which is very beneficial for image processing. This programming language requires two devices
to run at full efficiency, a host and a device. In previous years the host has been a regular computer,
while the device was generally a GPU. In order to make this project as portable as possible, the FPGA
that was used also contained two ARM cores that take on the role of host while the FPGA itself would
be the device

Full report (pdf)