Sandip Tiwari

Biography

Sandip Tiwari joined Cornell University in 1999 as Professor of Electrical and Computer Engineering and the Lester B. Knight Director of Cornell NanoScale Facility. Prior to that he was a Research Staff Member and Manager for Exploratory Devices and Device Modeling at the IBM Thomas J. Watson Research Center. He has held visiting and adjunct faculty appointments at University of Michigan (1988-89) and Columbia University (1993). He is a Fellow of IEEE and APS, and is a recipient of Young Scientist Award (18th Int'l. Symp. of GaAs & Related Compounds) and the Distinguished Alumni Award (IIT Kanpur). He is a past Associate Editor and Co-Guest Editor of IEEE Trans. on Electron Devices, is the founding Editor-in-Chief of IEEE Transactions on Nanotechnology, and is author of the text-book "Compound Semiconductor Device Physics." Over his career, he has explored the subjects of microwave devices and circuits, high speed electronic devices, optoelectronics, small and low power devices and their circuits and technology.

Research Interests

His current research interests are in small devices and their circuits, in ideas and technologies that allow continuing evolution of microelectronics in functional integration, and in interesting offshoots of small structures in other areas using silicon technology as a foundation. These subjects include: experimental and theoretical investigations of ultra-small transistor structures, use of nano-structures through device applications of single electron and reduced density of states effects, development of circuits that connect the small structures with the CMOS world, low power circuits, and three-dimensional integration for logic, memory, analog, and mixed-signal applications.

Recent Publications

• H. Silva, M. K. Kim, C. W. Kim and S. Tiwari, “Scaled Front and Back-Side Trapping SONOS Memories on SOI,” Tech. Dig. of  IEEE International Silicon-on-Insulator Conference, 105(2003).
• S. Tiwari, H. Silva, M. K. Kim, A. Kumar, and U. Avci, “Few Electron Memories: Finding the Compromise between Performance, Variability and Manufacturability at the Nano-Scale,” Invited Paper, Tech. Dig. of IEEE International Electron Devices Meeting, (2003).
• L. Xue, C. C. Liu, H-S Kim, S. Kim, and S. Tiwari,  “Three-Dimensional Integration: Technology, Use and Issues for Mixed-Signal Applications,” IEEE Trans. on Electron Devices, ED-50, No. 3,  601(2003).
• M.K. Kim, S.D. Chae, J.H. Kim, S.W. Yoon, Y.S. Jeong, H. Silva, S. Tiwari, and C.W. Kim, “Ultra-Short SONOS Memories,” Tech. Dig. of IEEE Silicon Nanoelectronics Workshop,  (2003).
• C. C. Liu, J.  Zhang, A. K. Datta, and S. Tiwari, “Heating Effects of Clock Drivers on Bulk, SOI, and 3D CMOS,” IEEE Electron Device Letters, V23, No.12, 716(2002).
• C. C. Liu and S. Tiwari, “Application of 3D CMOS Technology to SRAMs,” Proc. of IEEE SOI Conference, 68(2002).
• H. S. Kim, L. Xue, A. Kumar and S. Tiwari, “Fabrication and Electrical Properties of Buried Tungsten Structure for Direct Three-Dimensional Integration,” Proc. of Solid State Devices and Materials Meeting, 98(2002).
• S. Tiwari, H-S Kim, S. Kim, A. Kumar, C. C. Liu, and L. Xue, “Three-Dimensional Integration in Silicon Electronics,” Invited Paper, Proc. of IEEE LFE Conference on High Performance Devices, 24(2002).
• Kumar and S. Tiwari, “Scaling of Flash NVRAMs to 10’s of nm by Decoupling of Storage from Read/Sense using Back-Floating Gates,” IEEE Trans. on Nanotechnology, V1, No. 4, 247(2002).

• J. A. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser, and S. Tiwari, "Write, Erase and Storage times in Nano-Crystal Memories and the Role of Interface States and Percolation," Tech. Dig. of Int’l Electron Devices Meeting, p.375 (1999).
• S. Tiwari, P. Solomon, J. J. Welser, E. C. Jones, F. R. McFeely, and E. Cartier, "CMOS and Memories: From 100 nm to 10 nm!" Invited paper, Special Issue of Microelectronic Engineering, 46 p.3 (1999).
• S. Tiwari, J. J. Welser, A. Kumar, and S. Cohen, "Straddle Gate Transistor: A MOSFET in the Limit of Useful Field-Effect," Invited paper, Proc. of Workshop on Future Electronics and Int’l J. of High Speed Electronics and Systems, p.757 (1999).
• S. Tiwari, F. Rana, A. Kumar, J.J. Welser, and C.T. Black, "Role of Small Dimensions and Quantum Confinement in Small Silicon Memories," Proc. of Nanoelectronics Symp. of Electrochemical Society (1999).
• S. Tiwari and R. Nair , ‘‘Defect Tolerance in Computer Architecture: Towards Use of Massive Integration,’’ commentary in Physics World Oct. (1998).
• F. Rana, S. Tiwari, and J.J. Welser, "Modeling of Electron Tunneling Processes in Quantum-Dots Coupled to Field-Effect Transistors," Superlattices and Microstructures, Mar. (1998).
• J. J. Welser , S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, "Room Temperature Operation of Quantum-Dot Flash Memory," IEEE El. Dev. Letters, EDL18, p. 278 (1997).
• S. Tiwari, F. Rana , K. Chan, and W. Chen, "Single Charge and Confinement Effects in Nano-Crystal Memories," Appl. Phys. Lett., 69 p.1232 (1996).
• F. Rana, S. Tiwari, and D. Buchanan, "Self-consistent Modeling of Accumulation Layers and Calculation of Tunneling Currents through Very Thin Oxides," Appl. Phys. Lett., 69 1104 (1996).
• S. Tiwari, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, "A Silicon Nano-Crystals Based Memory,'' Appl. Phys. Lett. 68 1377 (1996).