Yi-Hsiang Sean Lai

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I am currently a PhD student in Cornell's Computer System Lab under Zhiru Zhang's adivce since 2016. I received my bachelor degree in Electrical Engineering from National Taiwan University in 2013 and my master degree in Electornics Engineering also from National Taiwan University in 2015 under Jie-Hong Roland Jiang's advice. My area of insterests includes but is not limited to electornic design automation (EDA), asynchronous system design and analysis, high-level sysynthesis (HLS), domain-specific languages (DSL), and machine learning.

Publications

  • Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang: Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 35(11): 1797-1810 (2016)
  • Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang: Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. ICCAD 2016: 5
  • Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang: Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. ICCAD 2015: 434-441
  • Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang: SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. ICCAD 2015: 442-449
  • Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang: A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. ICCAD 2015: 736-743
  • Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang: Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. DAC 2014: 192:1-192:6