.global image_mode image_mode: /* DATA ADDRESSES (post-compiler) for convenience PORTA 0x02 PORTB 0x05 PORTC 0x08 PORTD 0x0B PINA 0x00 (unused) PINB 0x03 (unused) PINC 0x06 (unused) PIND 0x09 SCREEN 640 pixels wide 480 pixels tall RESOLUTION 255 visible 'dots' wide, with each dot 2 pixels wide 480 visible 'dots' tall, with each dot 1 pixel tall TIMING each clock cycle takes ~39.72 nS using a 25.175 MHz crystal each line takes exactly 800 clock cycles and thus ~31.77 uS per line each screen prints exactly 512 lines and thus ~16.27 mS per screen for a 61.46 Hz screen refresh rate PORT ASSIGNMENTS from most significant to least significant bits PORTA/PINA: SRAM_Addr[7:0] //pixel number PORTB/PINB: SRAM_Addr[17:16], SRAM_OE, SRAM_WE, RGB_OUTPUT[4:0] PORTC/PINC: SRAM_Addr[15:8] //line number PORTD/PIND: V_sync, H_sync, TriState_OE, PushBtn_INPUT, RGB_INPUT[4:0] REGISTER ASSIGNMENTS r16: temporary reg for cursor drawing loop or joystick motion, status stored on stack r17: 1 r18: temporary reg for cursor buffer and joystick input r19: temporary reg for cursor buffer r20: Brush_Color[3:0], sometimes output PORTB[3:0] r21: Joystick_Timer r22: Printing_Pixel[7:0], output PORTA[7:0] r23: Debounce_Timer r24: Cursor_Printing_Y[7:0] r25: Cursor_Printing_Y[8] r26: Cursor_Printing_X[7:0] r27: Cursor_X[7:0] r28: Cursor_Y[7:0] r29: Cursor_Y[8] r30: Printing_Line[7:0], output PORTC[7:0] r31: Printing_Line[8], output PORTB[16] */ // save status register in r16,0x3F //1 push r16 //2 out 0x02,r0 ldi r17,48 out 0x05,r17 out 0x08,r0 ldi r17,224 out 0x0B,r17 /*sbi 0x05,4 //active low SRAM_WE sbi 0x05,5 //active low SRAM_OE sbi 0x0B,5 //active low tristate_EN sbi 0x0B,6 //active low H_sync sbi 0x0B,7 //active low V_sync*/ ldi r17,1 ldi r20,0 ldi r21,0 ldi r23,0 ldi r27,0 ldi r28,0 ldi r29,0 nop RESTART_SCREEN: //9 cycles ldi r16,0 ldi r18,0 ldi r19,0 ldi r22,0 ldi r24,0 ldi r25,0 ldi r26,0 ldi r30,0 ldi r31,0 RESTART_LINE: //**************************************************************************************** // **** HORIZONTAL AND VERTICAL SYNC = 75 CYCLES //**************************************************************************************** //9 cycles //assert v_sync low at the beginning of the first line //assert h_sync low at the beginning of every line cp r30,r0 cpc r31,r0 brne SKIP_V_LOW cbi 0x0B,7 //2; VERTICAL SYNC LOW rjmp H_LOW //2 SKIP_V_LOW: nop nop nop H_LOW: cbi 0x0B,6 //2; HORIZONTAL SYNC LOW //57 cycles nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop //9 cycles //return v_sync high at the beginning of the third line //return h_sync high at the beginning of every line cpi r30,2 cpc r31,r0 brne SKIP_V_HIGH sbi 0x0B,7 //2; VERTICAL SYNC HIGH rjmp H_HIGH //2 SKIP_V_HIGH: nop nop nop H_HIGH: sbi 0x0B,6 //2; HORIZONTAL SYNC HIGH //**************************************************************************************** // **** BACK PORCH = 72 CYCLES //**************************************************************************************** nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop //**************************************************************************************** // **** RGB BODY = 637 CYCLES //**************************************************************************************** //7 cycles nop nop nop nop nop nop nop //6 cycles //set most significant address bit cpi r31,1 breq SET_ADDRESS //1/2 cbi 0x05,6 //2 rjmp PRINT_RGB //2 SET_ADDRESS: sbi 0x05,6 //2 nop PRINT_RGB: //6 cycles //set remaining address bits ldi r22,0 out 0x02,r22 out 0x08,r30 cbi 0x05,5 //2 add r22,r17 //9 cycles //enable tristate for all lines between 2-479 cpi r31,0 breq CHECK_000_255 CHECK_256_511: cpi r30,224 brlo ENABLE_TRISTATE_1 rjmp DISABLE_TRISTATE CHECK_000_255: cpi r30,2 brlo DISABLE_TRISTATE rjmp ENABLE_TRISTATE_2 DISABLE_TRISTATE: nop rjmp BEGIN_RGB ENABLE_TRISTATE_1: nop nop ENABLE_TRISTATE_2: cbi 0x0B,5 //2 //509 cycles for 255 pixels //output address sequence to print 256 pixels across a row BEGIN_RGB: out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 add r22,r17 out 0x02,r22 //hide the final column //add r22,r17 //out 0x02,r22 //6 cycles //disable SRAM output and tristate sbi 0x05,5 //2 sbi 0x0B,5 //2 //compensate for two clock cycles lost by hiding column 255 nop nop //100 cycles nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop //**************************************************************************************** // **** FRONT PORCH = 16 CYCLES //**************************************************************************************** //7 cycles for RESTART_SCREEN //16 cycles for RESTART_LINE //increment line counter and return to start cpi r30,255 cpc r31,r17 breq SKIP_BELOW //1/2 adiw r30,1 //2 nop nop nop nop nop nop nop nop nop rjmp RESTART_LINE //2 SKIP_BELOW: nop rjmp RESTART_SCREEN //2 //NOTE: the following code is never reached // restore status register pop r16 //2 out 0x3F,r16 //1 clr r0 clr r1 // return from function ret