Cornell University ECE4760
Input Capture using PIO
Pi Pico RP2040

The PIO subsystem as input capture
The rp2040 has eight dedicated I/O state machines (PIO) each of which run a striped-down, single cycle, deterministic, assembly language from only 32 words of instruction memory per processor. Since the rp2040 does not have a hardware timer capture function, I decided to try to implement timer capture using one, then two PIO state machines. The typical timer capture uses hardware to copy the curent timer counter into a register for later cpu use. We ae gong to use a decrementing register on two PIO state machines, each of which ticks at one-half the clock rate of the system clock. But the two machines are phase-locked with one detecting edges one cycle after the other. This means that by using both machine time stamps, we can determine within one cycle when an edge occures.

Since the state machine clock rate is settable over a 1:65000 ratio, we can capture for as long a minute at 62.5 MHz (16 nSec resolution) or as long as two years at 1 KHz clock rate (1 mSec resolution). Since the PIO has deterministic, single cycle, execution we can enforce a uniform tick rate by decrementing the counter in every second instruction in each machine. An edge on an i/o pin can be detected by the PIO, causing the counter value to be copied to an 8-entry FIFO, serving as the capture register. The FIFO can throw an interrupt, or be polled, or simply read to get a recent time stamp.

The program outline for the two state machines:

1. The state machinse are executing a program with lots of jmp x-- because that is the only way to decriment a register.
   Every other instruction has to be a decrement to maintain an even clock rate.
   The first two statments load x with 0xffffffff.
   The we wait for a rising edge (while decrementing)
   When found, copies the x register to the in register, which is pushed onto the FIFO (while decrementing)
   The waits for a falling edge (while decrementing)
   When it finds a falling edge, it jumps back to waiting for a rising edge.(while decrementing)
   If the counter underflows. it is reset to high value.
   (The full program listing is below in the next section)
2. The second state machine runs the identical program, except for a one-cycle delay duirng initialization.
   The one-cycle phase shift means that one of the two machines will capture an edge any clock cycle.

A C program running on the ARM core allows a user to modify PWM max count (sets period-1), PWM dutycycle (sets pulse width),  PWM prescalar, PIO prescalar.
The current serial options are fairly cryptic because they were were meant just for testing.  The command line prompts for
PWM_cycles, PWM_duty, PWM_divider, PIO_divider
The values interact, so values are range checked again each other and the datasheet max values.
Error messages will notify you if you violate one of the conditions.

The following image shows two different sets of parameters. and the resulting actual PWM setting,
followed by a list from the 8-entry FIFO of time stamps, the difference between time stamps, and the
actual computed pulse periods from the differences. There is an inherent 1 PIO cycle uncertainty in the
results from each state machine, so the two machine time stamps need to be averaged. The image shows that
the averaged cycle count is accurate to one machine cycle (8 nSec here).

C code, PIOa, PIOb, project ZIP.

Single state machine version -- two cycle resolution
The single state machine scheme included:

• A configured and running PIO state machine executing a program with lots of jmp x-- because that is the only way to decriment a register.
  The first two statments load x with 0xffffffff.
  The we wait for a rising edge (while decrementing)
  When found, copies the x register to the in register, which is pushed onto the FIFO
  The waits for a falling edge (while decrementing)
  When it finds a falling edge, it jumps back to waiting for a rising edge.
  If the counter underflows. it is reset to high value.
  

  .wrap_target
  ; if the proram wraps to here, then 2^32 counts have ticked
  	set x 0x00		; init x timer 0x00000000 
  	mov x ~x		; NOT the bits into x 0xffffffff
  wait1:
  	jmp pin got1 	; wait for rising edge + delay a cycle
  	jmp x-- wait1	; loop is 2 cycles (two jmps+cycle-to-jmp) add one wait
  got1:
  	jmp x-- next0	; need to maintain timing
  next0:
  	in x 32			; send the counter to isr 
  	jmp x-- next1	; need to maintain timing
  next1:
         push noblock
  	jmp x-- wait0	; need to maintain timing
  	; now we need to debpunce to wait for a low level on the pin
  wait0:
  	jmp pin not0
  	jmp x-- wait1	; need to maintain timing
  ;next2:
  	;jmp wait1       ; got the 0, so wait for 1
  not0:
  	jmp x-- wait0	; loop is 2 cycles
  	;
  .wrap        

• A C program running on the ARM core which allows a user to modify PWM max count (sets period), PWM dutycycle (sets pulse width),  PWM prescalar, PIO prescalar.
  The current serial options are fairly cryptic because they were were meant just for testing.  The command line prompts for
  PWM_cycles, PWM_duty, PWM_divider, PIO_divider
  The values interact, so values are range checked again each other and the datasheet max values.
  Error messages will notify you if you violate one of the conditions.
  

The following image shows two different sets of parameters. and the resulting actual PWM setting,
followed by a list from the 8-entry FIFO of time stamps, the difference between time stamps, and the
actual computed pulse periods from the differences. There is an inherent 1 PIO cycle uncertainty in the
results, so realisticly, less than 10 or 20 pio cycle measurements are of limited accurcy without careful
calibration.

 

Code, ZIP of project, PIO code

Copyright Cornell University August 15, 2024