Cornell University ECE4760
C SDK on RP2040

Hunter Adams

Hunter Adams, as well as three MEng students, have been working to evaluate and characterize the RP2040 for potential use in ece4760.
The MEng work will be available next semester.

Setting up for C
Everything in this section comes from the Getting started with Raspberry Pi Pico for C/C++ development guide.
This contains all of the same content, just organized into an enumerated list based on our configurations.

Chained-DMA signal generator thru SPI DAC on RP2040
This project was meant to provide an objective thoough which to build understanding of DMA and SPI channels on the RP2040. For this project, Hunter chained two DMA channels. One of those channels is triggered by a timer which is configured to overflow at audio-rate ( 44kHz). This channel moves data from a sine table to the SPI transmit buffer. The SPI channel is configured to automatically transmit any new data which appears in its transmit buffer. The other DMA channel is chained to the first. When the first DMA channel finishes traversing the sine table, it triggers the second channel. This channel writes to the control registers of the first DMA channel.

Dual-core Direct Digital Synthesis (DDS) on RP2040
This project was meant to provide an objective through which to build understanding of multicore capabilities on the RP2040. For this project, Hunter instantiated a timer interrupt on both core 0 and core 1. Direct digital synthesis is performed separately on each core, and each core writes to a separate channel of the SPI DAC. The consequence is that the A output of the DAC is an an 800 Hz sine wave being generated on core 1, and the B output of the DAC is a 400 Hz sine wave being generated on core 0. Because the RP2040 buffers SPI writes, no spinlock is required to control each core's access to the SPI channel.

PIO Assembly VGA Driver for RP2040
This project uses three PIO state machines (synchronized with one another via interrupts) to drive a VGA screen. The pixel data to draw on the screen is communicated to the PIO state machines through a DMA channel. All of this pixel data is stored in a global character array. So, in the application part of the code, the user need only modify the contents of that global character array and the changes will be represented on the VGA screen, with no cpu involvment.

Realtime Audio FFT to VGA Display with RP2040
The ADC pacing timer is configured to gather samples at 10kHz, and to store those samples in the ADC FIFO (pre-shifted to 8 bits of significance). Whenever a sample appears in the ADC FIFO, the ADC's DREQ is asserted. DMA channel 2 is paced by the ADC DREQ, so that it automatically moves the ADC sample from the FIFO to a byte array. The DMA channel is configured to increment its write address so that it fills up each element of this 1024-element array with samples, at which point it signals to the C-code that it has finished. The C-code windows/copies this array to a local array, and then starts DMA channel 3. DMA channel 3 writes to the control registers of DMA channel 2 to reconfigure and restart it. While the next batch of samples is being gathered, the C code uses the local array to compute and display the FFT. It does so using the VGA PIO state machine described at length here.

Copyright Cornell University May 26, 2021