// Copyright 2010 Altera Corporation. All rights reserved. // Altera products are protected under numerous U.S. and foreign patents, // maskwork rights, copyrights and other intellectual property laws. // // This reference design file, and your use thereof, is subject to and governed // by the terms and conditions of the applicable Altera Reference Design // License Agreement (either as signed by you or found at www.altera.com). By // using this reference design file, you indicate your acceptance of such terms // and conditions between you and Altera Corporation. In the event that you do // not agree with such terms and conditions, you may not use the reference // design file and please promptly destroy any copies you have made. // // This reference design file is being provided on an "as-is" basis and as an // accommodation and therefore all warranties, representations or guarantees of // any kind (whether express, implied or statutory) including, without // limitation, warranties of merchantability, non-infringement, or fitness for // a particular purpose, are specifically disclaimed. By making this reference // design file available, Altera expressly does not recommend, suggest or // require that this reference design file be used in combination with any // other product not provided by Altera. ///////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps // baeckler - 12-05-2009 // one MLAB memory with support registers module mlab_fifo_cells ( input din_clk, input [19:0] din, input we, input [4:0] wraddr, input dout_clk, input [4:0] rdaddr, output [19:0] dout, input parity_err_in, output parity_err_out ); localparam BIT_WIDTH=20; localparam ADDR_WIDTH = 5; localparam DEPTH = 1 << ADDR_WIDTH; /////////////////////////// // input registers /////////////////////////// reg [BIT_WIDTH-1:0] din_reg = 0 /* synthesis preserve */; reg [BIT_WIDTH-1:0] din2_reg = 0 /* synthesis preserve */; reg [ADDR_WIDTH-1:0] wraddr_reg = 0 /* synthesis preserve */; reg [ADDR_WIDTH-1:0] wraddr2_reg = 0 /* synthesis preserve */; reg we_reg = 0 /* synthesis preserve */; always @(posedge din_clk) begin din_reg <= din; din2_reg <= din_reg; wraddr_reg <= wraddr; wraddr2_reg <= wraddr_reg; we_reg <= we; end /////////////////////////// // storage array - doesn't seem to work with direct 20 wide, need "for" /////////////////////////// wire [BIT_WIDTH-1:0] dout_wire; genvar i; generate for (i=0; i