Kraken CPU ISA (Stanford ee272, 2000)
This information is modified from a report by
Dennis Kim and Andrew Lin at Stanford.
|
Operation
|
Opcode
|
Destination Reg
|
Source Reg
|
Target Reg
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
7
|
6
|
5
|
4
|
3 |
2
|
1
|
0
|
| |
| ADD |
0
|
0
|
0
|
0
|
Rd
|
Rs
|
Rt
|
| SUB |
0
|
0
|
0
|
1
|
Rd
|
Rs
|
Rt
|
| AND |
0
|
0
|
1
|
0
|
Rd
|
Rs
|
Rt
|
| OR |
0
|
0
|
1
|
1
|
Rd
|
Rs
|
Rt
|
| XOR |
0
|
1
|
0
|
0
|
Rd
|
Rs
|
Rt
|
| NOT |
0
|
1
|
0
|
1
|
Rd
|
Rs
|
|
| SL |
0
|
1
|
1
|
0
|
Rd
|
Rs
|
|
| SR |
0
|
1
|
1
|
1
|
Rd
|
Rs
|
|
| |
| LI |
1
|
0
|
0
|
0
|
Rd
|
Immediate
|
| LW |
1
|
0
|
0
|
1
|
Rd
|
Rs
|
|
| SW |
1
|
0
|
1
|
0
|
|
Rs
|
Rt
|
| |
| BIZ |
1
|
0
|
1
|
1
|
Rs
|
Offset
|
| BNZ |
1
|
1
|
0
|
0
|
Rs
|
Offset
|
| |
| JAL |
1
|
1
|
0
|
1
|
Rd
|
Offset
|
| JMP |
1
|
1
|
1
|
0
|
|
Offset
|
| JR |
1
|
1
|
1
|
1
|
|
Rs
|
|
The Kraken features five instruction classes:
1. Arithmetic (Two's Complement) ALU operation (2 instructions)
2. Logical ALU operation (6)
3. Memory operations (3)
- LI: Rd <- (8@0)# immediate
4. Conditional Branch operations (2)
- BIZ: (Rs==0) -> (PC <- PC + Offset)
- BNZ: (Rs != 0) -> (PC <- PC + Offset)
5. Program Count Jump operations (3)
- JAL: (Rd <-PC : PC <- PC + Offset)