module DE1_SoC_Computer ( //////////////////////////////////// // FPGA Pins //////////////////////////////////// // Clock pins CLOCK_50, CLOCK2_50, CLOCK3_50, CLOCK4_50, // ADC ADC_CS_N, ADC_DIN, ADC_DOUT, ADC_SCLK, // Audio AUD_ADCDAT, AUD_ADCLRCK, AUD_BCLK, AUD_DACDAT, AUD_DACLRCK, AUD_XCK, // SDRAM DRAM_ADDR, DRAM_BA, DRAM_CAS_N, DRAM_CKE, DRAM_CLK, DRAM_CS_N, DRAM_DQ, DRAM_LDQM, DRAM_RAS_N, DRAM_UDQM, DRAM_WE_N, // I2C Bus for Configuration of the Audio and Video-In Chips FPGA_I2C_SCLK, FPGA_I2C_SDAT, // 40-Pin Headers GPIO_0, GPIO_1, // Seven Segment Displays HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, // IR IRDA_RXD, IRDA_TXD, // Pushbuttons KEY, // LEDs LEDR, // PS2 Ports PS2_CLK, PS2_DAT, PS2_CLK2, PS2_DAT2, // Slider Switches SW, // Video-In TD_CLK27, TD_DATA, TD_HS, TD_RESET_N, TD_VS, // VGA VGA_B, VGA_BLANK_N, VGA_CLK, VGA_G, VGA_HS, VGA_R, VGA_SYNC_N, VGA_VS, //////////////////////////////////// // HPS Pins //////////////////////////////////// // DDR3 SDRAM HPS_DDR3_ADDR, HPS_DDR3_BA, HPS_DDR3_CAS_N, HPS_DDR3_CKE, HPS_DDR3_CK_N, HPS_DDR3_CK_P, HPS_DDR3_CS_N, HPS_DDR3_DM, HPS_DDR3_DQ, HPS_DDR3_DQS_N, HPS_DDR3_DQS_P, HPS_DDR3_ODT, HPS_DDR3_RAS_N, HPS_DDR3_RESET_N, HPS_DDR3_RZQ, HPS_DDR3_WE_N, // Ethernet HPS_ENET_GTX_CLK, HPS_ENET_INT_N, HPS_ENET_MDC, HPS_ENET_MDIO, HPS_ENET_RX_CLK, HPS_ENET_RX_DATA, HPS_ENET_RX_DV, HPS_ENET_TX_DATA, HPS_ENET_TX_EN, // Flash HPS_FLASH_DATA, HPS_FLASH_DCLK, HPS_FLASH_NCSO, // Accelerometer HPS_GSENSOR_INT, // General Purpose I/O HPS_GPIO, // I2C HPS_I2C_CONTROL, HPS_I2C1_SCLK, HPS_I2C1_SDAT, HPS_I2C2_SCLK, HPS_I2C2_SDAT, // Pushbutton HPS_KEY, // LED HPS_LED, // SD Card HPS_SD_CLK, HPS_SD_CMD, HPS_SD_DATA, // SPI HPS_SPIM_CLK, HPS_SPIM_MISO, HPS_SPIM_MOSI, HPS_SPIM_SS, // UART HPS_UART_RX, HPS_UART_TX, // USB HPS_CONV_USB_N, HPS_USB_CLKOUT, HPS_USB_DATA, HPS_USB_DIR, HPS_USB_NXT, HPS_USB_STP ); //======================================================= // PARAMETER declarations //======================================================= //======================================================= // PORT declarations //======================================================= //////////////////////////////////// // FPGA Pins //////////////////////////////////// // Clock pins input CLOCK_50; input CLOCK2_50; input CLOCK3_50; input CLOCK4_50; // ADC inout ADC_CS_N; output ADC_DIN; input ADC_DOUT; output ADC_SCLK; // Audio input AUD_ADCDAT; inout AUD_ADCLRCK; inout AUD_BCLK; output AUD_DACDAT; inout AUD_DACLRCK; output AUD_XCK; // SDRAM output [12: 0] DRAM_ADDR; output [ 1: 0] DRAM_BA; output DRAM_CAS_N; output DRAM_CKE; output DRAM_CLK; output DRAM_CS_N; inout [15: 0] DRAM_DQ; output DRAM_LDQM; output DRAM_RAS_N; output DRAM_UDQM; output DRAM_WE_N; // I2C Bus for Configuration of the Audio and Video-In Chips output FPGA_I2C_SCLK; inout FPGA_I2C_SDAT; // 40-pin headers inout [35: 0] GPIO_0; inout [35: 0] GPIO_1; // Seven Segment Displays output [ 6: 0] HEX0; output [ 6: 0] HEX1; output [ 6: 0] HEX2; output [ 6: 0] HEX3; output [ 6: 0] HEX4; output [ 6: 0] HEX5; // IR input IRDA_RXD; output IRDA_TXD; // Pushbuttons input [ 3: 0] KEY; // LEDs output [ 9: 0] LEDR; // PS2 Ports inout PS2_CLK; inout PS2_DAT; inout PS2_CLK2; inout PS2_DAT2; // Slider Switches input [ 9: 0] SW; // Video-In input TD_CLK27; input [ 7: 0] TD_DATA; input TD_HS; output TD_RESET_N; input TD_VS; // VGA output [ 7: 0] VGA_B; output VGA_BLANK_N; output VGA_CLK; output [ 7: 0] VGA_G; output VGA_HS; output [ 7: 0] VGA_R; output VGA_SYNC_N; output VGA_VS; //////////////////////////////////// // HPS Pins //////////////////////////////////// // DDR3 SDRAM output [14: 0] HPS_DDR3_ADDR; output [ 2: 0] HPS_DDR3_BA; output HPS_DDR3_CAS_N; output HPS_DDR3_CKE; output HPS_DDR3_CK_N; output HPS_DDR3_CK_P; output HPS_DDR3_CS_N; output [ 3: 0] HPS_DDR3_DM; inout [31: 0] HPS_DDR3_DQ; inout [ 3: 0] HPS_DDR3_DQS_N; inout [ 3: 0] HPS_DDR3_DQS_P; output HPS_DDR3_ODT; output HPS_DDR3_RAS_N; output HPS_DDR3_RESET_N; input HPS_DDR3_RZQ; output HPS_DDR3_WE_N; // Ethernet output HPS_ENET_GTX_CLK; inout HPS_ENET_INT_N; output HPS_ENET_MDC; inout HPS_ENET_MDIO; input HPS_ENET_RX_CLK; input [ 3: 0] HPS_ENET_RX_DATA; input HPS_ENET_RX_DV; output [ 3: 0] HPS_ENET_TX_DATA; output HPS_ENET_TX_EN; // Flash inout [ 3: 0] HPS_FLASH_DATA; output HPS_FLASH_DCLK; output HPS_FLASH_NCSO; // Accelerometer inout HPS_GSENSOR_INT; // General Purpose I/O inout [ 1: 0] HPS_GPIO; // I2C inout HPS_I2C_CONTROL; inout HPS_I2C1_SCLK; inout HPS_I2C1_SDAT; inout HPS_I2C2_SCLK; inout HPS_I2C2_SDAT; // Pushbutton inout HPS_KEY; // LED inout HPS_LED; // SD Card output HPS_SD_CLK; inout HPS_SD_CMD; inout [ 3: 0] HPS_SD_DATA; // SPI output HPS_SPIM_CLK; input HPS_SPIM_MISO; output HPS_SPIM_MOSI; inout HPS_SPIM_SS; // UART input HPS_UART_RX; output HPS_UART_TX; // USB inout HPS_CONV_USB_N; input HPS_USB_CLKOUT; inout [ 7: 0] HPS_USB_DATA; input HPS_USB_DIR; input HPS_USB_NXT; output HPS_USB_STP; //======================================================= // REG/WIRE declarations //======================================================= wire [15: 0] hex3_hex0; //wire [15: 0] hex5_hex4; //assign HEX0 = ~hex3_hex0[ 6: 0]; // hex3_hex0[ 6: 0]; //assign HEX1 = ~hex3_hex0[14: 8]; //assign HEX2 = ~hex3_hex0[22:16]; //assign HEX3 = ~hex3_hex0[30:24]; assign HEX4 = 7'b1111111; assign HEX5 = 7'b1111111; assign HEX3 = 7'b1111111; assign HEX2 = 7'b1111111; assign HEX1 = 7'b1111111; assign HEX0 = 7'b1111111; // Memory control reg [9:0] string_mem_addr ; reg signed [31:0] string_mem_read_data ; reg signed [31:0] string_mem_write_data ; reg string_mem_we ; // parameters reg [7:0] string_length ; // integer 20 to 200 reg signed [26:0] rho ; // 27 bit 2:25 fix reg signed [26:0] eta ; // 27 bit 2:25 fix // current solver computational target element U(i) reg [7:0] string_index ; // nearest neighbor stack // string memory reads are pushed onto stack_top reg signed [26:0] stack_top, stack_middle, stack_bottom ; // Previous time step Uold(i) // memory offset to previous time step array is 256 //reg [9:0] string_last_mem_addr ; // The newly calculated Unew(i) and the last value Uold(i) reg signed [26:0] Unew, Uold ; // computation control reg [7:0] state ; wire CLOCK_100 ; // state machine reset if it locks wire reset; assign reset = ~KEY[0] ; // three multipliers for rho, (1-eta*dt/2) wire signed [26:0] rho_x_sum, eta_x_Uold, eta_x_Unew ; // rho*(U(i+1) - 2*U(i) + U(i-1)) signed_mult_2_25 mult_rho(rho_x_sum, rho, stack_top-(stack_middle<<1)+stack_bottom) ; // (1-eta*dt/2) * U(i-1) signed_mult_2_25 mult_eta1(eta_x_Uold, eta, Uold) ; // (1-eta*dt/2) * Unew signed_mult_2_25 mult_eta2(eta_x_Unew, eta, Unew) ; // debugging state assign LEDR = state ; // =============================================== // === String read/execute state machine ========= // =============================================== // // On solver trigger signal from HPS: // read rho, eta, string length // --string_length is memory location 200 // --rho is memory location 201 // --ets is memory location 202 // read 3 string buffer memory locations and push onto stack // Iterate thru string // -- generating and storing new Ui // -- push new value onto stack // Set solver done flag for HPS always @(posedge CLOCK_100) begin //CLOCK_50 // reset state machine and read/write controls if (reset) begin state <= 0 ; string_mem_we <= 0 ; end else begin //================= // get trigger // === trigger === // set up read for trigger from HPS if (state==8'd0) begin string_mem_addr <= 10'd255 ; string_mem_we <= 1'b0 ; state <= 8'd1 ; // wait for read end // wait read trigger from HPS if (state==8'd1) begin state <= 8'd2 ; // wait for read end // read trigger from HPS if (state==8'd2) begin if (string_mem_read_data==1) begin state <= 8'd10 ; // got the trigger! end else begin state <= 8'd0 ; end end // ================= // read parameters // === length === // got the trigger, read string length if (state == 8'd10) begin string_mem_addr <= 10'd200 ; string_mem_we <= 1'b0 ; state <= 8'd11 ; // end // wait read length if (state == 8'd11) begin state <= 8'd12 ; // wait for read end // read read length if (state == 8'd12) begin string_length <= string_mem_read_data ; state <= 8'd13 ; // wait for read end // === rho === // read rho if (state == 8'd13) begin string_mem_addr <= 10'd201 ; string_mem_we <= 1'b0 ; state <= 8'd14 ; // end // wait rho if (state == 8'd14) begin state <= 8'd15 ; // wait for read end // read rho if (state == 8'd15) begin rho <= string_mem_read_data ; state <= 8'd16 ; // wait for read end // === eta === // read eta if (state == 8'd16) begin string_mem_addr <= 10'd202 ; // c/v error -- 201 string_mem_we <= 1'b0 ; state <= 8'd17 ; // end // wait eta if (state == 8'd17) begin state <= 8'd18 ; // wait for read end // read eta if (state == 8'd18) begin eta <= string_mem_read_data ; // c/v error -- rho state <= 8'd20 ; // wait for read end // ========================= // === initialize string === // to do this we need to fill a 3-element stack // with the Ui and it's nearest neighbors // push index zero onto the stack (i-1 neighbor) // push index one onto the stack (index i to update) // push index two onto the stack (i+1 neigbor) // Also need to read the Uold value for a separate array if (state == 8'd20) begin // first index to actually update is one, index ZERO is fixed at zero string_index <= 8'd1 ; // push zero onto the stack (string end is always zero) stack_top <= 32'd0 ; //stack_middle <= stack_top ; //stack_bottom <= stack_middle ; // === set up read for first mem location === string_mem_addr <= 10'd1 ; string_mem_we <= 1'b0 ; state <= 8'd21 ; end // wait for i=1 value if (state == 8'd21) begin state <= 8'd22 ; end // read U(1) value and push stack if (state == 8'd22) begin stack_top <= string_mem_read_data ; stack_middle <= stack_top ; //stack_middle <= stack_top ; state <= 8'd23 ; end // === end of initialzation === // === loop-back point for next i === // === set up read U(i+1) value === if (state == 8'd23) begin string_mem_addr <= string_index + 8'd1 ; string_mem_we <= 1'b0 ; state <= 8'd24 ; end // wait for i+1 value if (state == 8'd24) begin state <= 8'd25 ; end // push i+1 value onto stack if (state == 8'd25) begin stack_top <= string_mem_read_data ; // holds U(i+1) stack_middle <= stack_top ; // holds U(i) stack_bottom <= stack_middle ; // holds U(i-1) state <= 8'd26 ; end // === set up read Uold value === if (state == 8'd26) begin string_mem_addr <= string_index + 10'd256 ; string_mem_we <= 1'b0 ; state <= 8'd27 ; end // wait for Uold value if (state == 8'd27) begin state <= 8'd28 ; end // get Uold(i) value if (state == 8'd28) begin Uold <= string_mem_read_data ; // holds U(i+1) state <= 8'd40 ; // typo 30 end // === start calculation === if (state == 8'd40) begin // Unew = rho*(U(i+1) - 2*U(i) + U(i-1)) - eta*U(i-1) Unew <= rho_x_sum - eta_x_Uold + (stack_middle<<1) ; state <= 8'd41 ; end // if (state == 8'd41) begin // final new value Unew <= eta_x_Unew ; state <= 8'd42 ; end // === write back Unew === if (state == 8'd42) begin // write final new value string_mem_addr <= string_index ; string_mem_write_data <= Unew ; string_mem_we <= 1'b1 ; state <= 8'd43 ; end // === write back current U(i) to Uold(i) array // write stack middle to Uold(i) array if (state == 8'd43) begin // write Uold(i) value string_mem_addr <= string_index + 10'd256 ; // stack_middle still holds U(i) string_mem_write_data <= stack_middle ; string_mem_we <= 1'b1 ; state <= 8'd45 ; end // === decide if at end of string === // if so, signal HPS // otherwise, loop back // jump back to finish string -- OR -- signal HPS if (state == 8'd45) begin // if at string end, // signal HPS by clearing trigger flag at addr 255 // then go to trigger wait state 0 // dont update position string_length-1 which should stay zero if (string_index == (string_length-8'd3)) begin // should be 8'd2??? string_mem_addr <= 10'd255 ; string_mem_write_data <= 0 ; string_mem_we <= 1'b1 ; state <= 8'd0 ; end // otherwise loop back to incrment along the string else begin // increment string count string_index <= string_index + 8'd1 ; // disable write string_mem_we <= 1'b0 ; // jump back to U(i+1) read wait state state <= 8'd23 ; // typo d24 end end // if (state == 8'd45) end // NOT reset else end // always @(posedge state_clock) //======================================================= // Structural coding //======================================================= Computer_System The_System ( //////////////////////////////////// // FPGA Side //////////////////////////////////// // Global signals .system_pll_ref_clk_clk (CLOCK_50), .system_pll_ref_reset_reset (1'b0), // AV Config .av_config_SCLK (FPGA_I2C_SCLK), .av_config_SDAT (FPGA_I2C_SDAT), // Audio Subsystem .audio_pll_ref_clk_clk (CLOCK3_50), .audio_pll_ref_reset_reset (1'b0), .audio_clk_clk (AUD_XCK), .audio_ADCDAT (AUD_ADCDAT), .audio_ADCLRCK (AUD_ADCLRCK), .audio_BCLK (AUD_BCLK), .audio_DACDAT (AUD_DACDAT), .audio_DACLRCK (AUD_DACLRCK), // bus-master state machine interface .string_buffer_1_s2_address (string_mem_addr), .string_buffer_1_s2_chipselect (1'b1), .string_buffer_1_s2_clken (1'b1), .string_buffer_1_s2_write (string_mem_we), .string_buffer_1_s2_readdata (string_mem_read_data), .string_buffer_1_s2_writedata (string_mem_write_data), .string_buffer_1_s2_byteenable (4'b1111), // clock output .system_pll_sdram_clk_clk (CLOCK_100), //////////////////////////////////// // HPS Side //////////////////////////////////// // DDR3 SDRAM .memory_mem_a (HPS_DDR3_ADDR), .memory_mem_ba (HPS_DDR3_BA), .memory_mem_ck (HPS_DDR3_CK_P), .memory_mem_ck_n (HPS_DDR3_CK_N), .memory_mem_cke (HPS_DDR3_CKE), .memory_mem_cs_n (HPS_DDR3_CS_N), .memory_mem_ras_n (HPS_DDR3_RAS_N), .memory_mem_cas_n (HPS_DDR3_CAS_N), .memory_mem_we_n (HPS_DDR3_WE_N), .memory_mem_reset_n (HPS_DDR3_RESET_N), .memory_mem_dq (HPS_DDR3_DQ), .memory_mem_dqs (HPS_DDR3_DQS_P), .memory_mem_dqs_n (HPS_DDR3_DQS_N), .memory_mem_odt (HPS_DDR3_ODT), .memory_mem_dm (HPS_DDR3_DM), .memory_oct_rzqin (HPS_DDR3_RZQ), // Ethernet .hps_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N), .hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK), .hps_io_hps_io_emac1_inst_TXD0 (HPS_ENET_TX_DATA[0]), .hps_io_hps_io_emac1_inst_TXD1 (HPS_ENET_TX_DATA[1]), .hps_io_hps_io_emac1_inst_TXD2 (HPS_ENET_TX_DATA[2]), .hps_io_hps_io_emac1_inst_TXD3 (HPS_ENET_TX_DATA[3]), .hps_io_hps_io_emac1_inst_RXD0 (HPS_ENET_RX_DATA[0]), .hps_io_hps_io_emac1_inst_MDIO (HPS_ENET_MDIO), .hps_io_hps_io_emac1_inst_MDC (HPS_ENET_MDC), .hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV), .hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN), .hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK), .hps_io_hps_io_emac1_inst_RXD1 (HPS_ENET_RX_DATA[1]), .hps_io_hps_io_emac1_inst_RXD2 (HPS_ENET_RX_DATA[2]), .hps_io_hps_io_emac1_inst_RXD3 (HPS_ENET_RX_DATA[3]), // Flash .hps_io_hps_io_qspi_inst_IO0 (HPS_FLASH_DATA[0]), .hps_io_hps_io_qspi_inst_IO1 (HPS_FLASH_DATA[1]), .hps_io_hps_io_qspi_inst_IO2 (HPS_FLASH_DATA[2]), .hps_io_hps_io_qspi_inst_IO3 (HPS_FLASH_DATA[3]), .hps_io_hps_io_qspi_inst_SS0 (HPS_FLASH_NCSO), .hps_io_hps_io_qspi_inst_CLK (HPS_FLASH_DCLK), // Accelerometer .hps_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT), //.adc_sclk (ADC_SCLK), //.adc_cs_n (ADC_CS_N), //.adc_dout (ADC_DOUT), //.adc_din (ADC_DIN), // General Purpose I/O .hps_io_hps_io_gpio_inst_GPIO40 (HPS_GPIO[0]), .hps_io_hps_io_gpio_inst_GPIO41 (HPS_GPIO[1]), // I2C .hps_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL), .hps_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT), .hps_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK), .hps_io_hps_io_i2c1_inst_SDA (HPS_I2C2_SDAT), .hps_io_hps_io_i2c1_inst_SCL (HPS_I2C2_SCLK), // Pushbutton .hps_io_hps_io_gpio_inst_GPIO54 (HPS_KEY), // LED .hps_io_hps_io_gpio_inst_GPIO53 (HPS_LED), // SD Card .hps_io_hps_io_sdio_inst_CMD (HPS_SD_CMD), .hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]), .hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]), .hps_io_hps_io_sdio_inst_CLK (HPS_SD_CLK), .hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]), .hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]), // SPI .hps_io_hps_io_spim1_inst_CLK (HPS_SPIM_CLK), .hps_io_hps_io_spim1_inst_MOSI (HPS_SPIM_MOSI), .hps_io_hps_io_spim1_inst_MISO (HPS_SPIM_MISO), .hps_io_hps_io_spim1_inst_SS0 (HPS_SPIM_SS), // UART .hps_io_hps_io_uart0_inst_RX (HPS_UART_RX), .hps_io_hps_io_uart0_inst_TX (HPS_UART_TX), // USB .hps_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N), .hps_io_hps_io_usb1_inst_D0 (HPS_USB_DATA[0]), .hps_io_hps_io_usb1_inst_D1 (HPS_USB_DATA[1]), .hps_io_hps_io_usb1_inst_D2 (HPS_USB_DATA[2]), .hps_io_hps_io_usb1_inst_D3 (HPS_USB_DATA[3]), .hps_io_hps_io_usb1_inst_D4 (HPS_USB_DATA[4]), .hps_io_hps_io_usb1_inst_D5 (HPS_USB_DATA[5]), .hps_io_hps_io_usb1_inst_D6 (HPS_USB_DATA[6]), .hps_io_hps_io_usb1_inst_D7 (HPS_USB_DATA[7]), .hps_io_hps_io_usb1_inst_CLK (HPS_USB_CLKOUT), .hps_io_hps_io_usb1_inst_STP (HPS_USB_STP), .hps_io_hps_io_usb1_inst_DIR (HPS_USB_DIR), .hps_io_hps_io_usb1_inst_NXT (HPS_USB_NXT) ); endmodule /////////////////////////////////////////////////// //// signed mult of 2.25 format 2'comp //////////// /////////////////////////////////////////////////// module signed_mult_2_25 (out, a, b); output [26:0] out; input signed [26:0] a; input signed [26:0] b; wire signed [26:0] out; wire signed [53:0] mult_out; assign mult_out = a * b; // 1 bit sign with 26 bits from bit25 to bit50 assign out = {mult_out[53], mult_out[50:25]}; endmodule ////////////////////////////////////////////////// ////////////////////////////////////////////////// //////////// Sin Wave ROM Table ////////////// ////////////////////////////////////////////////// // produces a 2's comp, 16-bit, approximation // of a sine wave, given an input phase (address) module sync_rom (clock, address, sine); input clock; input [7:0] address; output [15:0] sine; reg signed [15:0] sine; always@(posedge clock) begin case(address) 8'h00: sine = 16'h0000 ; 8'h01: sine = 16'h0192 ; 8'h02: sine = 16'h0323 ; 8'h03: sine = 16'h04b5 ; 8'h04: sine = 16'h0645 ; 8'h05: sine = 16'h07d5 ; 8'h06: sine = 16'h0963 ; 8'h07: sine = 16'h0af0 ; 8'h08: sine = 16'h0c7c ; 8'h09: sine = 16'h0e05 ; 8'h0a: sine = 16'h0f8c ; 8'h0b: sine = 16'h1111 ; 8'h0c: sine = 16'h1293 ; 8'h0d: sine = 16'h1413 ; 8'h0e: sine = 16'h158f ; 8'h0f: sine = 16'h1708 ; 8'h10: sine = 16'h187d ; 8'h11: sine = 16'h19ef ; 8'h12: sine = 16'h1b5c ; 8'h13: sine = 16'h1cc5 ; 8'h14: sine = 16'h1e2a ; 8'h15: sine = 16'h1f8b ; 8'h16: sine = 16'h20e6 ; 8'h17: sine = 16'h223c ; 8'h18: sine = 16'h238d ; 8'h19: sine = 16'h24d9 ; 8'h1a: sine = 16'h261f ; 8'h1b: sine = 16'h275f ; 8'h1c: sine = 16'h2899 ; 8'h1d: sine = 16'h29cc ; 8'h1e: sine = 16'h2afa ; 8'h1f: sine = 16'h2c20 ; 8'h20: sine = 16'h2d40 ; 8'h21: sine = 16'h2e59 ; 8'h22: sine = 16'h2f6b ; 8'h23: sine = 16'h3075 ; 8'h24: sine = 16'h3178 ; 8'h25: sine = 16'h3273 ; 8'h26: sine = 16'h3366 ; 8'h27: sine = 16'h3452 ; 8'h28: sine = 16'h3535 ; 8'h29: sine = 16'h3611 ; 8'h2a: sine = 16'h36e4 ; 8'h2b: sine = 16'h37ae ; 8'h2c: sine = 16'h3870 ; 8'h2d: sine = 16'h3929 ; 8'h2e: sine = 16'h39da ; 8'h2f: sine = 16'h3a81 ; 8'h30: sine = 16'h3b1f ; 8'h31: sine = 16'h3bb5 ; 8'h32: sine = 16'h3c41 ; 8'h33: sine = 16'h3cc4 ; 8'h34: sine = 16'h3d3d ; 8'h35: sine = 16'h3dad ; 8'h36: sine = 16'h3e14 ; 8'h37: sine = 16'h3e70 ; 8'h38: sine = 16'h3ec4 ; 8'h39: sine = 16'h3f0d ; 8'h3a: sine = 16'h3f4d ; 8'h3b: sine = 16'h3f83 ; 8'h3c: sine = 16'h3fb0 ; 8'h3d: sine = 16'h3fd2 ; 8'h3e: sine = 16'h3feb ; 8'h3f: sine = 16'h3ffa ; 8'h40: sine = 16'h3fff ; 8'h41: sine = 16'h3ffa ; 8'h42: sine = 16'h3feb ; 8'h43: sine = 16'h3fd2 ; 8'h44: sine = 16'h3fb0 ; 8'h45: sine = 16'h3f83 ; 8'h46: sine = 16'h3f4d ; 8'h47: sine = 16'h3f0d ; 8'h48: sine = 16'h3ec4 ; 8'h49: sine = 16'h3e70 ; 8'h4a: sine = 16'h3e14 ; 8'h4b: sine = 16'h3dad ; 8'h4c: sine = 16'h3d3d ; 8'h4d: sine = 16'h3cc4 ; 8'h4e: sine = 16'h3c41 ; 8'h4f: sine = 16'h3bb5 ; 8'h50: sine = 16'h3b1f ; 8'h51: sine = 16'h3a81 ; 8'h52: sine = 16'h39da ; 8'h53: sine = 16'h3929 ; 8'h54: sine = 16'h3870 ; 8'h55: sine = 16'h37ae ; 8'h56: sine = 16'h36e4 ; 8'h57: sine = 16'h3611 ; 8'h58: sine = 16'h3535 ; 8'h59: sine = 16'h3452 ; 8'h5a: sine = 16'h3366 ; 8'h5b: sine = 16'h3273 ; 8'h5c: sine = 16'h3178 ; 8'h5d: sine = 16'h3075 ; 8'h5e: sine = 16'h2f6b ; 8'h5f: sine = 16'h2e59 ; 8'h60: sine = 16'h2d40 ; 8'h61: sine = 16'h2c20 ; 8'h62: sine = 16'h2afa ; 8'h63: sine = 16'h29cc ; 8'h64: sine = 16'h2899 ; 8'h65: sine = 16'h275f ; 8'h66: sine = 16'h261f ; 8'h67: sine = 16'h24d9 ; 8'h68: sine = 16'h238d ; 8'h69: sine = 16'h223c ; 8'h6a: sine = 16'h20e6 ; 8'h6b: sine = 16'h1f8b ; 8'h6c: sine = 16'h1e2a ; 8'h6d: sine = 16'h1cc5 ; 8'h6e: sine = 16'h1b5c ; 8'h6f: sine = 16'h19ef ; 8'h70: sine = 16'h187d ; 8'h71: sine = 16'h1708 ; 8'h72: sine = 16'h158f ; 8'h73: sine = 16'h1413 ; 8'h74: sine = 16'h1293 ; 8'h75: sine = 16'h1111 ; 8'h76: sine = 16'h0f8c ; 8'h77: sine = 16'h0e05 ; 8'h78: sine = 16'h0c7c ; 8'h79: sine = 16'h0af0 ; 8'h7a: sine = 16'h0963 ; 8'h7b: sine = 16'h07d5 ; 8'h7c: sine = 16'h0645 ; 8'h7d: sine = 16'h04b5 ; 8'h7e: sine = 16'h0323 ; 8'h7f: sine = 16'h0192 ; 8'h80: sine = 16'h0000 ; 8'h81: sine = 16'hfe6e ; 8'h82: sine = 16'hfcdd ; 8'h83: sine = 16'hfb4b ; 8'h84: sine = 16'hf9bb ; 8'h85: sine = 16'hf82b ; 8'h86: sine = 16'hf69d ; 8'h87: sine = 16'hf510 ; 8'h88: sine = 16'hf384 ; 8'h89: sine = 16'hf1fb ; 8'h8a: sine = 16'hf074 ; 8'h8b: sine = 16'heeef ; 8'h8c: sine = 16'hed6d ; 8'h8d: sine = 16'hebed ; 8'h8e: sine = 16'hea71 ; 8'h8f: sine = 16'he8f8 ; 8'h90: sine = 16'he783 ; 8'h91: sine = 16'he611 ; 8'h92: sine = 16'he4a4 ; 8'h93: sine = 16'he33b ; 8'h94: sine = 16'he1d6 ; 8'h95: sine = 16'he075 ; 8'h96: sine = 16'hdf1a ; 8'h97: sine = 16'hddc4 ; 8'h98: sine = 16'hdc73 ; 8'h99: sine = 16'hdb27 ; 8'h9a: sine = 16'hd9e1 ; 8'h9b: sine = 16'hd8a1 ; 8'h9c: sine = 16'hd767 ; 8'h9d: sine = 16'hd634 ; 8'h9e: sine = 16'hd506 ; 8'h9f: sine = 16'hd3e0 ; 8'ha0: sine = 16'hd2c0 ; 8'ha1: sine = 16'hd1a7 ; 8'ha2: sine = 16'hd095 ; 8'ha3: sine = 16'hcf8b ; 8'ha4: sine = 16'hce88 ; 8'ha5: sine = 16'hcd8d ; 8'ha6: sine = 16'hcc9a ; 8'ha7: sine = 16'hcbae ; 8'ha8: sine = 16'hcacb ; 8'ha9: sine = 16'hc9ef ; 8'haa: sine = 16'hc91c ; 8'hab: sine = 16'hc852 ; 8'hac: sine = 16'hc790 ; 8'had: sine = 16'hc6d7 ; 8'hae: sine = 16'hc626 ; 8'haf: sine = 16'hc57f ; 8'hb0: sine = 16'hc4e1 ; 8'hb1: sine = 16'hc44b ; 8'hb2: sine = 16'hc3bf ; 8'hb3: sine = 16'hc33c ; 8'hb4: sine = 16'hc2c3 ; 8'hb5: sine = 16'hc253 ; 8'hb6: sine = 16'hc1ec ; 8'hb7: sine = 16'hc190 ; 8'hb8: sine = 16'hc13c ; 8'hb9: sine = 16'hc0f3 ; 8'hba: sine = 16'hc0b3 ; 8'hbb: sine = 16'hc07d ; 8'hbc: sine = 16'hc050 ; 8'hbd: sine = 16'hc02e ; 8'hbe: sine = 16'hc015 ; 8'hbf: sine = 16'hc006 ; 8'hc0: sine = 16'hc001 ; 8'hc1: sine = 16'hc006 ; 8'hc2: sine = 16'hc015 ; 8'hc3: sine = 16'hc02e ; 8'hc4: sine = 16'hc050 ; 8'hc5: sine = 16'hc07d ; 8'hc6: sine = 16'hc0b3 ; 8'hc7: sine = 16'hc0f3 ; 8'hc8: sine = 16'hc13c ; 8'hc9: sine = 16'hc190 ; 8'hca: sine = 16'hc1ec ; 8'hcb: sine = 16'hc253 ; 8'hcc: sine = 16'hc2c3 ; 8'hcd: sine = 16'hc33c ; 8'hce: sine = 16'hc3bf ; 8'hcf: sine = 16'hc44b ; 8'hd0: sine = 16'hc4e1 ; 8'hd1: sine = 16'hc57f ; 8'hd2: sine = 16'hc626 ; 8'hd3: sine = 16'hc6d7 ; 8'hd4: sine = 16'hc790 ; 8'hd5: sine = 16'hc852 ; 8'hd6: sine = 16'hc91c ; 8'hd7: sine = 16'hc9ef ; 8'hd8: sine = 16'hcacb ; 8'hd9: sine = 16'hcbae ; 8'hda: sine = 16'hcc9a ; 8'hdb: sine = 16'hcd8d ; 8'hdc: sine = 16'hce88 ; 8'hdd: sine = 16'hcf8b ; 8'hde: sine = 16'hd095 ; 8'hdf: sine = 16'hd1a7 ; 8'he0: sine = 16'hd2c0 ; 8'he1: sine = 16'hd3e0 ; 8'he2: sine = 16'hd506 ; 8'he3: sine = 16'hd634 ; 8'he4: sine = 16'hd767 ; 8'he5: sine = 16'hd8a1 ; 8'he6: sine = 16'hd9e1 ; 8'he7: sine = 16'hdb27 ; 8'he8: sine = 16'hdc73 ; 8'he9: sine = 16'hddc4 ; 8'hea: sine = 16'hdf1a ; 8'heb: sine = 16'he075 ; 8'hec: sine = 16'he1d6 ; 8'hed: sine = 16'he33b ; 8'hee: sine = 16'he4a4 ; 8'hef: sine = 16'he611 ; 8'hf0: sine = 16'he783 ; 8'hf1: sine = 16'he8f8 ; 8'hf2: sine = 16'hea71 ; 8'hf3: sine = 16'hebed ; 8'hf4: sine = 16'hed6d ; 8'hf5: sine = 16'heeef ; 8'hf6: sine = 16'hf074 ; 8'hf7: sine = 16'hf1fb ; 8'hf8: sine = 16'hf384 ; 8'hf9: sine = 16'hf510 ; 8'hfa: sine = 16'hf69d ; 8'hfb: sine = 16'hf82b ; 8'hfc: sine = 16'hf9bb ; 8'hfd: sine = 16'hfb4b ; 8'hfe: sine = 16'hfcdd ; 8'hff: sine = 16'hfe6e ; endcase end endmodule ///// end /////////////////////////////////