| Operation | opcode |
Dest Reg (11:8) |
Source Reg (7:4) |
Source Reg (3:0) |
effect |
|---|---|---|---|---|---|
| ADD | 0 |
Rd |
Rs |
Rt |
Rd < Rs + Rt |
| SUB | 1 |
Rd |
Rs |
Rt |
Rd < Rs - Rt |
| AND | 2 |
Rd |
Rs |
Rt |
Rd < Rs & Rt |
| OR | 3 |
Rd |
Rs |
Rt |
Rd < Rs | Rt |
| XOR | 4 |
Rd |
Rs |
Rt |
Rd < Rs ^ Rt |
NOT |
5 |
Rd |
Rs |
Rd < ~Rs |
|
SR |
6 |
Rd |
Rs |
Rd < Rs >> 1 |
|
LIL |
7 |
Rd |
imm(8-bit) |
Rd < (10@0)#imm |
|
LIH |
8 |
Rd |
imm(8-bit) |
Rd < ((2@0)#imm#(8@0)) | Rd |
|
| LWR | 9 |
Rd |
Rs |
Rd < Mem[Rs] |
|
LWD |
a |
Rd |
addr(8-bit) |
Rd < Mem[addr] |
|
SWR |
b |
Rd |
Rs |
Mem[Rs] < Rd |
|
SWD |
c |
Rd |
addr(8-bit) |
Mem[addr] <- Rd |
|
BIZ |
d |
Rd |
addr(8-bit) |
(Rd==0) -> (PC < addr) |
|
| BNZ | e |
Rd |
addr(8-bit) |
(Rd!=0) -> (PC < addr) |
|
| JAL | f |
Rd |
addr(8-bit) |
(Rd < PC : PC < addr) |
|
JR |
10 |
Rd |
PC < Rd |
||
| IN | 11 |
Rd |
Rs |
Rd < (i/o register Rs) |
|
OUT |
12 |
Rd |
Rs |
(i/o register Rd) < Rs |
|
| MUL | 13 |
Rd |
Rs |
Rt |
Rd < Rs * Rt (2:16 fractions) |
MULL |
14 |
Rd |
Rs |
Rt |
Rd < low(Rs * Rt) (integer) |
MULH |
15 |
Rd |
Rs |
Rt |
Rd < hi(Rs * Rt) (integer) |
Memory:
16-word x 18-bit dual ported register file
256 18-bit words of data
256 18-bit instructions
Implied instructions (if R0==0):
| Implied | actual | effect |
|---|---|---|
| CLR Rd | XOR Rd Rd Rd |
Rd < 0 |
| MOV Rd Rs | ADD Rd Rs R0 |
Rd < Rs |
| NOP | ADD R0 R0 R0 |
none |
| JMP addr | BIZ R0 addr |
PC < addr |
| NEG Rd Rt | SUB R0 Rt |
Rd < -Rt |
| SL Rd Rs | ADD Rd Rs Rs |
Rd < Rs << 1 |