// -------------------------------------------------------------------- // Copyright (c) 2005 by Terasic Technologies Inc. // -------------------------------------------------------------------- // // Permission: // // Terasic grants permission to use and modify this code for use // in synthesis for all Terasic Development Boards and Altera Development // Kits made by Terasic. Other use of this code, including the selling // ,duplication, or modification of any portion is strictly prohibited. // // Disclaimer: // // This VHDL/Verilog or C/C++ source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user's responsibility to verify their design for // consistency and functionality through the use of formal // verification methods. Terasic provides no warranty regarding the use // or functionality of this code. // // -------------------------------------------------------------------- // // Terasic Technologies Inc // 356 Fu-Shin E. Rd Sec. 1. JhuBei City, // HsinChu County, Taiwan // 302 // // web: http://www.terasic.com/ // email: support@terasic.com // // -------------------------------------------------------------------- // // Major Functions: DE2 Default Bitstream // TOP LEVEL FILE // module DE2_CCD ( //////////////////// Clock Input //////////////////// CLOCK_27, // 27 MHz CLOCK_50, // 50 MHz EXT_CLOCK, // External Clock //////////////////// Push Button //////////////////// KEY, // Pushbutton[3:0] //////////////////// DPDT Switch //////////////////// SW, // Toggle Switch[17:0] //////////////////// 7-SEG Dispaly //////////////////// HEX0, // Seven Segment Digit 0 HEX1, // Seven Segment Digit 1 HEX2, // Seven Segment Digit 2 HEX3, // Seven Segment Digit 3 HEX4, // Seven Segment Digit 4 HEX5, // Seven Segment Digit 5 HEX6, // Seven Segment Digit 6 HEX7, // Seven Segment Digit 7 //////////////////////// LED //////////////////////// LEDG, // LED Green[8:0] LEDR, // LED Red[17:0] //////////////////////// UART //////////////////////// UART_TXD, // UART Transmitter UART_RXD, // UART Receiver //////////////////////// IRDA //////////////////////// IRDA_TXD, // IRDA Transmitter IRDA_RXD, // IRDA Receiver ///////////////////// SDRAM Interface //////////////// DRAM_DQ, // SDRAM Data bus 16 Bits DRAM_ADDR, // SDRAM Address bus 12 Bits DRAM_LDQM, // SDRAM Low-byte Data Mask DRAM_UDQM, // SDRAM High-byte Data Mask DRAM_WE_N, // SDRAM Write Enable DRAM_CAS_N, // SDRAM Column Address Strobe DRAM_RAS_N, // SDRAM Row Address Strobe DRAM_CS_N, // SDRAM Chip Select DRAM_BA_0, // SDRAM Bank Address 0 DRAM_BA_1, // SDRAM Bank Address 0 DRAM_CLK, // SDRAM Clock DRAM_CKE, // SDRAM Clock Enable //////////////////// Flash Interface //////////////// FL_DQ, // FLASH Data bus 8 Bits FL_ADDR, // FLASH Address bus 22 Bits FL_WE_N, // FLASH Write Enable FL_RST_N, // FLASH Reset FL_OE_N, // FLASH Output Enable FL_CE_N, // FLASH Chip Enable //////////////////// SRAM Interface //////////////// SRAM_DQ, // SRAM Data bus 16 Bits SRAM_ADDR, // SRAM Address bus 18 Bits SRAM_UB_N, // SRAM High-byte Data Mask SRAM_LB_N, // SRAM Low-byte Data Mask SRAM_WE_N, // SRAM Write Enable SRAM_CE_N, // SRAM Chip Enable SRAM_OE_N, // SRAM Output Enable //////////////////// ISP1362 Interface //////////////// OTG_DATA, // ISP1362 Data bus 16 Bits OTG_ADDR, // ISP1362 Address 2 Bits OTG_CS_N, // ISP1362 Chip Select OTG_RD_N, // ISP1362 Write OTG_WR_N, // ISP1362 Read OTG_RST_N, // ISP1362 Reset OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable OTG_INT0, // ISP1362 Interrupt 0 OTG_INT1, // ISP1362 Interrupt 1 OTG_DREQ0, // ISP1362 DMA Request 0 OTG_DREQ1, // ISP1362 DMA Request 1 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1 //////////////////// LCD Module 16X2 //////////////// LCD_ON, // LCD Power ON/OFF LCD_BLON, // LCD Back Light ON/OFF LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read LCD_EN, // LCD Enable LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data LCD_DATA, // LCD Data bus 8 bits //////////////////// SD_Card Interface //////////////// SD_DAT, // SD Card Data SD_DAT3, // SD Card Data 3 SD_CMD, // SD Card Command Signal SD_CLK, // SD Card Clock //////////////////// USB JTAG link //////////////////// TDI, // CPLD -> FPGA (data in) TCK, // CPLD -> FPGA (clk) TCS, // CPLD -> FPGA (CS) TDO, // FPGA -> CPLD (data out) //////////////////// I2C //////////////////////////// I2C_SDAT, // I2C Data I2C_SCLK, // I2C Clock //////////////////// PS2 //////////////////////////// PS2_DAT, // PS2 Data PS2_CLK, // PS2 Clock //////////////////// VGA //////////////////////////// VGA_CLK, // VGA Clock VGA_HS, // VGA H_SYNC VGA_VS, // VGA V_SYNC VGA_BLANK, // VGA BLANK VGA_SYNC, // VGA SYNC VGA_R, // VGA Red[9:0] VGA_G, // VGA Green[9:0] VGA_B, // VGA Blue[9:0] //////////// Ethernet Interface //////////////////////// ENET_DATA, // DM9000A DATA bus 16Bits ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data ENET_CS_N, // DM9000A Chip Select ENET_WR_N, // DM9000A Write ENET_RD_N, // DM9000A Read ENET_RST_N, // DM9000A Reset ENET_INT, // DM9000A Interrupt ENET_CLK, // DM9000A Clock 25 MHz //////////////// Audio CODEC //////////////////////// AUD_ADCLRCK, // Audio CODEC ADC LR Clock AUD_ADCDAT, // Audio CODEC ADC Data AUD_DACLRCK, // Audio CODEC DAC LR Clock AUD_DACDAT, // Audio CODEC DAC Data AUD_BCLK, // Audio CODEC Bit-Stream Clock AUD_XCK, // Audio CODEC Chip Clock //////////////// TV Decoder //////////////////////// TD_DATA, // TV Decoder Data bus 8 bits TD_HS, // TV Decoder H_SYNC TD_VS, // TV Decoder V_SYNC TD_RESET, // TV Decoder Reset //////////////////// GPIO //////////////////////////// GPIO_0, // GPIO Connection 0 GPIO_1 // GPIO Connection 1 ); //////////////////////// Clock Input //////////////////////// input CLOCK_27; // 27 MHz input CLOCK_50; // 50 MHz input EXT_CLOCK; // External Clock //////////////////////// Push Button //////////////////////// input [3:0] KEY; // Pushbutton[3:0] //////////////////////// DPDT Switch //////////////////////// input [17:0] SW; // Toggle Switch[17:0] //////////////////////// 7-SEG Dispaly //////////////////////// output [6:0] HEX0; // Seven Segment Digit 0 output [6:0] HEX1; // Seven Segment Digit 1 output [6:0] HEX2; // Seven Segment Digit 2 output [6:0] HEX3; // Seven Segment Digit 3 output [6:0] HEX4; // Seven Segment Digit 4 output [6:0] HEX5; // Seven Segment Digit 5 output [6:0] HEX6; // Seven Segment Digit 6 output [6:0] HEX7; // Seven Segment Digit 7 //////////////////////////// LED //////////////////////////// output [8:0] LEDG; // LED Green[8:0] output [17:0] LEDR; // LED Red[17:0] //////////////////////////// UART //////////////////////////// output UART_TXD; // UART Transmitter input UART_RXD; // UART Receiver //////////////////////////// IRDA //////////////////////////// output IRDA_TXD; // IRDA Transmitter input IRDA_RXD; // IRDA Receiver /////////////////////// SDRAM Interface //////////////////////// inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits output DRAM_LDQM; // SDRAM Low-byte Data Mask output DRAM_UDQM; // SDRAM High-byte Data Mask output DRAM_WE_N; // SDRAM Write Enable output DRAM_CAS_N; // SDRAM Column Address Strobe output DRAM_RAS_N; // SDRAM Row Address Strobe output DRAM_CS_N; // SDRAM Chip Select output DRAM_BA_0; // SDRAM Bank Address 0 output DRAM_BA_1; // SDRAM Bank Address 0 output DRAM_CLK; // SDRAM Clock output DRAM_CKE; // SDRAM Clock Enable //////////////////////// Flash Interface //////////////////////// inout [7:0] FL_DQ; // FLASH Data bus 8 Bits output [21:0] FL_ADDR; // FLASH Address bus 22 Bits output FL_WE_N; // FLASH Write Enable output FL_RST_N; // FLASH Reset output FL_OE_N; // FLASH Output Enable output FL_CE_N; // FLASH Chip Enable //////////////////////// SRAM Interface //////////////////////// inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits output SRAM_UB_N; // SRAM High-byte Data Mask output SRAM_LB_N; // SRAM Low-byte Data Mask output SRAM_WE_N; // SRAM Write Enable output SRAM_CE_N; // SRAM Chip Enable output SRAM_OE_N; // SRAM Output Enable //////////////////// ISP1362 Interface //////////////////////// inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits output OTG_CS_N; // ISP1362 Chip Select output OTG_RD_N; // ISP1362 Write output OTG_WR_N; // ISP1362 Read output OTG_RST_N; // ISP1362 Reset output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable input OTG_INT0; // ISP1362 Interrupt 0 input OTG_INT1; // ISP1362 Interrupt 1 input OTG_DREQ0; // ISP1362 DMA Request 0 input OTG_DREQ1; // ISP1362 DMA Request 1 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1 //////////////////// LCD Module 16X2 //////////////////////////// inout [7:0] LCD_DATA; // LCD Data bus 8 bits output LCD_ON; // LCD Power ON/OFF output LCD_BLON; // LCD Back Light ON/OFF output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read output LCD_EN; // LCD Enable output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data //////////////////// SD Card Interface //////////////////////// inout SD_DAT; // SD Card Data inout SD_DAT3; // SD Card Data 3 inout SD_CMD; // SD Card Command Signal output SD_CLK; // SD Card Clock //////////////////////// I2C //////////////////////////////// inout I2C_SDAT; // I2C Data output I2C_SCLK; // I2C Clock //////////////////////// PS2 //////////////////////////////// input PS2_DAT; // PS2 Data input PS2_CLK; // PS2 Clock //////////////////// USB JTAG link //////////////////////////// input TDI; // CPLD -> FPGA (data in) input TCK; // CPLD -> FPGA (clk) input TCS; // CPLD -> FPGA (CS) output TDO; // FPGA -> CPLD (data out) //////////////////////// VGA //////////////////////////// output VGA_CLK; // VGA Clock output VGA_HS; // VGA H_SYNC output VGA_VS; // VGA V_SYNC output VGA_BLANK; // VGA BLANK output VGA_SYNC; // VGA SYNC output [9:0] VGA_R; // VGA Red[9:0] output [9:0] VGA_G; // VGA Green[9:0] output [9:0] VGA_B; // VGA Blue[9:0] //////////////// Ethernet Interface //////////////////////////// inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data output ENET_CS_N; // DM9000A Chip Select output ENET_WR_N; // DM9000A Write output ENET_RD_N; // DM9000A Read output ENET_RST_N; // DM9000A Reset input ENET_INT; // DM9000A Interrupt output ENET_CLK; // DM9000A Clock 25 MHz //////////////////// Audio CODEC //////////////////////////// inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock input AUD_ADCDAT; // Audio CODEC ADC Data inout AUD_DACLRCK; // Audio CODEC DAC LR Clock output AUD_DACDAT; // Audio CODEC DAC Data inout AUD_BCLK; // Audio CODEC Bit-Stream Clock output AUD_XCK; // Audio CODEC Chip Clock //////////////////// TV Devoder //////////////////////////// input [7:0] TD_DATA; // TV Decoder Data bus 8 bits input TD_HS; // TV Decoder H_SYNC input TD_VS; // TV Decoder V_SYNC output TD_RESET; // TV Decoder Reset //////////////////////// GPIO //////////////////////////////// inout [35:0] GPIO_0; // GPIO Connection 0 inout [35:0] GPIO_1; // GPIO Connection 1 //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------------------------- assign LCD_ON = 1'b1; assign LCD_BLON = 1'b1; // All inout port turn to tri-state assign DRAM_DQ = 16'hzzzz; assign FL_DQ = 8'hzz; assign SRAM_DQ = 16'hzzzz; assign OTG_DATA = 16'hzzzz; assign SD_DAT = 1'bz; assign ENET_DATA = 16'hzzzz; assign GPIO_0 = 36'hzzzzzzzzz; assign GPIO_1 = 36'hzzzzzzzzz; assign TD_RESET = 1'b1; // Allow 27 MHz input ////////////////////////////////////////////////////////////////////// //////////////////////////////////// //VGA variables to write to SRAM reg [17:0] addr_reg; //memory address register for SRAM reg [15:0] data_reg; //memory data register for SRAM reg we ; //write enable for SRAM reg [7:0] led; //debug led register wire VGA_CTRL_CLK; wire AUD_CTRL_CLK; wire [9:0] mVGA_R; //display values wire [9:0] mVGA_G; wire [9:0] mVGA_B; wire [9:0] Coord_X, Coord_Y; //display coods wire Read; //////////////////////////////////////// /////////////////////////////////////////////////////////////////////// // CCD stuff wire [9:0] CCD_DATA; wire CCD_SDAT; wire CCD_SCLK; wire CCD_FLASH; wire CCD_FVAL; wire CCD_LVAL; wire CCD_PIXCLK; reg CCD_MCLK; // CCD Master Clock wire [9:0] mCCD_DATA; wire mCCD_DVAL; wire mCCD_DVAL_d; wire [9:0] mCCD_R; wire [9:0] mCCD_G; wire [9:0] mCCD_B; reg [9:0] rCCD_DATA; reg rCCD_LVAL; reg rCCD_FVAL; wire [9:0] sCCD_BW; wire sCCD_DVAL; //data coming off the SDRAM wire [15:0] Read_DATA1; wire [15:0] Read_DATA2; //X and Y coordinates of stuff wire [10:0] X_Cont; wire [10:0] Y_Cont; wire [31:0] Frame_Cont; //the frame counter //processing algorithm wire SDRAM_READ_CLOCK; wire SDRAM_READ_LOGIC; //turn on delay reset wire DLY_RST_0; wire DLY_RST_1; wire DLY_RST_2; //global reset button signal wire reset; wire startCAM; wire stopCAM; assign LEDG = led; //it also so happens this will be our signal to begin processing //(when this goes low, we know we have 2 images) assign RAM_WRITE_SELECT_BLOCK = Frame_Cont[0] ? 0 : 1; //write every other frame to a different ram // SRAM_control assign SRAM_ADDR = addr_reg; assign SRAM_DQ = (we)? 16'hzzzz : data_reg ; assign SRAM_UB_N = 0; // hi byte select enabled assign SRAM_LB_N = 0; // lo byte select enabled assign SRAM_CE_N = 0; // chip is enabled assign SRAM_WE_N = we; // write when ZERO assign SRAM_OE_N = 0; //output enable is overidden by WE // For Sensor 1 assign CCD_DATA[0] = GPIO_1[0]; assign CCD_DATA[1] = GPIO_1[1]; assign CCD_DATA[2] = GPIO_1[5]; assign CCD_DATA[3] = GPIO_1[3]; assign CCD_DATA[4] = GPIO_1[2]; assign CCD_DATA[5] = GPIO_1[4]; assign CCD_DATA[6] = GPIO_1[6]; assign CCD_DATA[7] = GPIO_1[7]; assign CCD_DATA[8] = GPIO_1[8]; assign CCD_DATA[9] = GPIO_1[9]; assign GPIO_1[11] = CCD_MCLK; assign GPIO_1[15] = CCD_SDAT; assign GPIO_1[14] = CCD_SCLK; assign CCD_FVAL = GPIO_1[13]; assign CCD_LVAL = GPIO_1[12]; assign CCD_PIXCLK = GPIO_1[10]; //SOME INPUT assign reset = ~KEY[0]; assign startCAM = ~KEY[2]; assign stopCAM = ~KEY[3]; //ready signal for value for Edge display wire startEdgeDetect; //assign VGA_CTRL_CLK= CCD_MCLK; //assign VGA_CLK = ~CCD_MCLK; always@(posedge CLOCK_50) CCD_MCLK <= ~CCD_MCLK; //25 Mhz always@(posedge CCD_PIXCLK) begin rCCD_DATA <= CCD_DATA; rCCD_LVAL <= CCD_LVAL; rCCD_FVAL <= CCD_FVAL; end // Show SRAM on the VGA //SRAM ORGANIZATION //we have a BW image, so we only need 10 bits of the SRAM. //the top 10 bits are the image data //the next three indicate whether to make the whole pixel RED, GREEN and BLUE respecitvely //if the lower bits respectively bits are set, then it's all R, G, or B. //otherwise, it's greyscale, b/c RGB all have the same values SRAM_DQ[15:6] assign mVGA_R = SRAM_DQ[5] ? 10'hFFFF : SRAM_DQ[15:6]; assign mVGA_G = SRAM_DQ[4] ? 10'hFFFF : SRAM_DQ[15:6]; assign mVGA_B = SRAM_DQ[3] ? 10'hFFFF : SRAM_DQ[15:6]; /* assign mVGA_R = {Read_DATA1[9:0]}; assign mVGA_G = {Read_DATA1[9:0]}; assign mVGA_B = {Read_DATA1[9:0]}; */ //generate VGA clock //adjust VGA_Audio_PLL setting to obtain desire VGA speed //default 25.2MHz, better quality at 43.2MHz VGA_Audio_PLL p1 ( .areset(~DLY_RST_2),.inclk0(CLOCK_27),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK) ); VGA_Controller u1 ( // Host Side .iCursor_RGB_EN(4'b0111), .oAddress(mVGA_ADDR), .oCoord_X(Coord_X), .oCoord_Y(Coord_Y), .iRed(mVGA_R), .iGreen(mVGA_G), .iBlue(mVGA_B), // VGA Side .oVGA_R(VGA_R), .oVGA_G(VGA_G), .oVGA_B(VGA_B), .oVGA_H_SYNC(VGA_HS), .oVGA_V_SYNC(VGA_VS), .oVGA_SYNC(VGA_SYNC), .oVGA_BLANK(VGA_BLANK), // Control Signal .iCLK(VGA_CTRL_CLK), .iRST_N(DLY_RST_0) ); Reset_Delay u2 ( .iCLK(CLOCK_50), .iRST(KEY[0]), .oRST_0(DLY_RST_0), .oRST_1(DLY_RST_1), .oRST_2(DLY_RST_2) ); //camera module CCD_Capture u3 ( .oDATA(mCCD_DATA), .oDVAL(mCCD_DVAL), .oX_Cont(X_Cont), .oY_Cont(Y_Cont), .oFrame_Cont(Frame_Cont), .iDATA(rCCD_DATA), .iFVAL(rCCD_FVAL), .iLVAL(rCCD_LVAL), .iSTART(startCAM), .iEND(stopCAM), .iCLK(CCD_PIXCLK), .iRST(DLY_RST_1)); //convert raw data to RGB RAW2RGB u4 ( .oRed(mCCD_R), .oGreen(mCCD_G), .oBlue(mCCD_B), .oDVAL(mCCD_DVAL_d), .iX_Cont(X_Cont), .iY_Cont(Y_Cont), .iDATA(mCCD_DATA), .iDVAL(mCCD_DVAL), .iCLK(CCD_PIXCLK), .iRST(DLY_RST_1)); SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1), .oSEG2(HEX2),.oSEG3(HEX3), .oSEG4(HEX4),.oSEG5(HEX5), .oSEG6(HEX6),.oSEG7(HEX7), .iDIG({16'h0000,SADTemp}) ); //.iDIG({Frame_Cont}) ); // //this is completely differnet now // the ram is partitioned between two images //specifically, image 1 is in the first 640*512 block // image 2 is offset by h100000 (~the offset required // for the blanking pixel clock cycles) reg [31:0] pixcnt; reg FRMA; always @(posedge CCD_PIXCLK) begin if (~DLY_RST_1) begin pixcnt<=0; FRMA<=0; end else if (sCCD_DVAL) begin if (pixcnt < ((640*512)-1)) pixcnt<=pixcnt+1; else begin pixcnt<=0; FRMA<=~FRMA; end end end Sdram_Control_4Port u6 ( // HOST Side .REF_CLK(CLOCK_50), .RESET_N(1'b1), //never reset // FIFO Write Side 1 (image 1) .WR1_DATA({6'b000000,sCCD_BW[9:0]}), .WR1(sCCD_DVAL & FRMA), //.WR1(sCCD_DVAL), .WR1_ADDR(0), .WR1_MAX_ADDR(640*512), .WR1_LENGTH(9'h100), //256 .WR1_LOAD(!DLY_RST_0), .WR1_CLK(CCD_PIXCLK), // FIFO Write Side 2 (image 2) .WR2_DATA({6'h0,sCCD_BW[9:0]}), .WR2(sCCD_DVAL & ~FRMA), .WR2_ADDR(22'h100000), .WR2_MAX_ADDR(22'h100000+640*512), .WR2_LENGTH(9'h100), .WR2_LOAD(!DLY_RST_0), .WR2_CLK(CCD_PIXCLK), // FIFO Read Side 1 .RD1_DATA(Read_DATA1), .RD1(SDRAM_READ_LOGIC), //.RD1(Read), //.RD1() .RD1_ADDR(640*16), //16 bit offset is for the differing resolutions .RD1_MAX_ADDR(640*496), .RD1_LENGTH(9'h100), .RD1_LOAD(!DLY_RST_0), .RD1_CLK(SDRAM_READ_CLOCK), //.RD1_CLK(VGA_CTRL_CLK) //.RD1_CLK() // FIFO Read Side 2 .RD2_DATA(Read_DATA2), .RD2(SDRAM_READ_LOGIC), .RD2_ADDR(22'h100000+640*16), .RD2_MAX_ADDR(22'h100000+640*496), .RD2_LENGTH(9'h100), .RD2_LOAD(!DLY_RST_0), .RD2_CLK(SDRAM_READ_CLOCK), // SDRAM Side .SA(DRAM_ADDR), .BA({DRAM_BA_1,DRAM_BA_0}), .CS_N(DRAM_CS_N), .CKE(DRAM_CKE), .RAS_N(DRAM_RAS_N), .CAS_N(DRAM_CAS_N), .WE_N(DRAM_WE_N), .DQ(DRAM_DQ), .DQM({DRAM_UDQM,DRAM_LDQM}), .SDR_CLK(DRAM_CLK) ); //configures the I2C registers on the camera (gain, etc.) //modified explosure to higher value I2C_CCD_Config u7 ( // Host Side .iCLK(CLOCK_50), .iRST_N(KEY[1]), .iExposure(SW[15:0]), // I2C Side .I2C_SCLK(CCD_SCLK), .I2C_SDAT(CCD_SDAT) ); //modified to convert to black and white Mirror_Col u8 ( // Input Side .iCCD_R(mCCD_R), .iCCD_G(mCCD_G), .iCCD_B(mCCD_B), .iCCD_DVAL(mCCD_DVAL_d), .iCCD_PIXCLK(CCD_PIXCLK), .iRST_N(DLY_RST_1), // Output Side .oCCD_BW(sCCD_BW), .oCCD_DVAL(sCCD_DVAL), //.oLED(LEDR) ); wire [17:0] VGASRAM_ADDR; wire [15:0] VGASRAM_DATA; //performs block correlation and generates edges sobel u9 ( .iReset(reset), .iClock(CLOCK_50), .oLED(LEDR), //the images from the SDRAM .oSDRAM_READ_CLOCK(SDRAM_READ_CLOCK), //data clock on the sdram (each cycle gets a new word) .oSDRAM_READ_LOGIC(SDRAM_READ_LOGIC), //set high when data is wanted .iSDRAM_IMAGE1(Read_DATA1), //data from image 1 .iSDRAM_IMAGE2(Read_DATA2), //data from image 2 //the output to the VGA .oVGASRAM_ADDR(VGASRAM_ADDR), //address of VGA output SRAM (320x240) .oVGASRAM_DATA(VGASRAM_DATA), //data for " " .iVGA_OK_TO_WRITE(VGA_OK_TO_WRITE), //signal indicating it is OK to write to the SRAM .iVGA_CTRL_CLK(VGA_CTRL_CLK), .oStartEdgeDetect(startEdgeDetect), //ready signal for VGA .isw(SW[17:0]) //threshold values ); wire VGA_OK_TO_WRITE; assign VGA_OK_TO_WRITE = (~VGA_VS | ~VGA_HS) & (~reset); //this will go high during blanking reg lock; always @ (posedge VGA_CTRL_CLK) begin if (reset) //synch reset assumes KEY0 is held down 1/60 second begin //clear the screen addr_reg <= {Coord_X[9:1],Coord_Y[9:1]} ; // [19:0] we <= 1'b0; //write some memory data_reg <= 16'h0000; //write all zeros (black) led <= 8'b11111111; end //modify display during sync and edge calculation is active //data from sobel edge detection else if (VGA_OK_TO_WRITE & startEdgeDetect) begin addr_reg <= VGASRAM_ADDR; lock <= 1'b1; data_reg <= VGASRAM_DATA; we <= 1'b0; led <= 8'b00001111; end //show display when not blanking, //which implies we=1 (not enabled); and use VGA module address else if (~VGA_OK_TO_WRITE) begin we <= 1'b1; addr_reg <= {Coord_X[9:1],Coord_Y[9:1]} ; lock <= 1'b0; end end endmodule