The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design fifo.v. The design fifo.v has a depth of 8 words of 24 bits each. The output of the fifo is registered. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.
The above waveform shows the behavior of the design under normal read and write conditions .