| userDefinedSettings |
|
| tightlyCoupledInstructionMaster3MapParam |
|
| tightlyCoupledInstructionMaster3AddrWidth |
1 |
| tightlyCoupledInstructionMaster2MapParam |
|
| tightlyCoupledInstructionMaster2AddrWidth |
1 |
| tightlyCoupledInstructionMaster1MapParam |
|
| tightlyCoupledInstructionMaster1AddrWidth |
1 |
| tightlyCoupledInstructionMaster0MapParam |
|
| tightlyCoupledInstructionMaster0AddrWidth |
1 |
| tightlyCoupledDataMaster3MapParam |
|
| tightlyCoupledDataMaster3AddrWidth |
1 |
| tightlyCoupledDataMaster2MapParam |
|
| tightlyCoupledDataMaster2AddrWidth |
1 |
| tightlyCoupledDataMaster1MapParam |
|
| tightlyCoupledDataMaster1AddrWidth |
1 |
| tightlyCoupledDataMaster0MapParam |
|
| tightlyCoupledDataMaster0AddrWidth |
1 |
| setting_showUnpublishedSettings |
false |
| setting_showInternalSettings |
false |
| setting_shadowRegisterSets |
0 |
| setting_preciseSlaveAccessErrorException |
false |
| setting_preciseIllegalMemAccessException |
false |
| setting_preciseDivisionErrorException |
false |
| setting_performanceCounter |
false |
| setting_perfCounterWidth |
_32 |
| setting_interruptControllerType |
Internal |
| setting_illegalMemAccessDetection |
false |
| setting_illegalInstructionsTrap |
false |
| setting_fullWaveformSignals |
false |
| setting_extraExceptionInfo |
false |
| setting_exportPCB |
false |
| setting_debugSimGen |
false |
| setting_clearXBitsLDNonBypass |
true |
| setting_branchPredictionType |
Automatic |
| setting_bit31BypassDCache |
true |
| setting_bigEndian |
false |
| setting_bhtPtrSz |
_8 |
| setting_bhtIndexPcOnly |
false |
| setting_avalonDebugPortPresent |
false |
| setting_alwaysEncrypt |
true |
| setting_allowFullAddressRange |
false |
| setting_activateTrace |
true |
| setting_activateTestEndChecker |
false |
| setting_activateMonitors |
true |
| setting_activateModelChecker |
false |
| setting_HDLSimCachesCleared |
true |
| setting_HBreakTest |
false |
| resetSlave |
sdram.s1 |
| resetOffset |
0 |
| muldiv_multiplierType |
EmbeddedMulFast |
| muldiv_divider |
false |
| mpu_useLimit |
false |
| mpu_numOfInstRegion |
8 |
| mpu_numOfDataRegion |
8 |
| mpu_minInstRegionSize |
_12 |
| mpu_minDataRegionSize |
_12 |
| mpu_enabled |
false |
| mmu_uitlbNumEntries |
_4 |
| mmu_udtlbNumEntries |
_6 |
| mmu_tlbPtrSz |
_7 |
| mmu_tlbNumWays |
_16 |
| mmu_processIDNumBits |
_8 |
| mmu_enabled |
false |
| mmu_autoAssignTlbPtrSz |
true |
| mmu_TLBMissExcSlave |
|
| mmu_TLBMissExcOffset |
0 |
| manuallyAssignCpuID |
false |
| internalIrqMaskSystemInfo |
3 |
| instSlaveMapParam |
<address-map><slave name='cpu.jtag_debug_module' start='0x800' end='0x1000' /><slave name='sdram.s1' start='0x2000000' end='0x2800000' /></address-map> |
| instAddrWidth |
26 |
| impl |
Small |
| icache_size |
_4096 |
| icache_ramBlockType |
Automatic |
| icache_numTCIM |
_0 |
| icache_burstType |
None |
| exceptionSlave |
sdram.s1 |
| exceptionOffset |
32 |
| deviceFeaturesSystemInfo |
M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 |
| deviceFamilyName |
Cyclone II |
| debug_triggerArming |
true |
| debug_level |
Level1 |
| debug_jtagInstanceID |
0 |
| debug_embeddedPLL |
true |
| debug_debugReqSignals |
false |
| debug_assignJtagInstanceID |
false |
| debug_OCIOnchipTrace |
_128 |
| dcache_size |
_2048 |
| dcache_ramBlockType |
Automatic |
| dcache_omitDataMaster |
false |
| dcache_numTCDM |
_0 |
| dcache_lineSize |
_32 |
| dcache_bursts |
false |
| dataSlaveMapParam |
<address-map><slave name='ps2_event_type.s1' start='0x0' end='0x10' /><slave name='event_has_been_read.s1' start='0x10' end='0x20' /><slave name='new_event_ready.s1' start='0x20' end='0x30' /><slave name='jtag_uart.avalon_jtag_slave' start='0x30' end='0x38' /><slave name='TIMER_0.s1' start='0x40' end='0x60' /><slave name='lcd_0.control_slave' start='0x60' end='0x70' /><slave name='sram_we_n.s1' start='0x70' end='0x80' /><slave name='sram_addr.s1' start='0x80' end='0x90' /><slave name='sram_dq.s1' start='0x90' end='0xA0' /><slave name='cur_x.s1' start='0xA0' end='0xB0' /><slave name='cur_y.s1' start='0xB0' end='0xC0' /><slave name='play.s1' start='0xC0' end='0xD0' /><slave name='obj.s1' start='0xD0' end='0xE0' /><slave name='en0.s1' start='0xE0' end='0xF0' /><slave name='en1.s1' start='0xF0' end='0x100' /><slave name='en2.s1' start='0x100' end='0x110' /><slave name='period0.s1' start='0x110' end='0x120' /><slave name='period1.s1' start='0x120' end='0x130' /><slave name='period2.s1' start='0x130' end='0x140' /><slave name='period_gol.s1' start='0x140' end='0x150' /><slave name='speed0.s1' start='0x150' end='0x160' /><slave name='speed1.s1' start='0x160' end='0x170' /><slave name='speed2.s1' start='0x170' end='0x180' /><slave name='tone_mode.s1' start='0x180' end='0x190' /><slave name='set_sel0.s1' start='0x190' end='0x1A0' /><slave name='set_sel1.s1' start='0x1A0' end='0x1B0' /><slave name='set_sel2.s1' start='0x1B0' end='0x1C0' /><slave name='cpu.jtag_debug_module' start='0x800' end='0x1000' /><slave name='sdram.s1' start='0x2000000' end='0x2800000' /></address-map> |
| dataAddrWidth |
26 |
| customInstSlavesSystemInfo |
<info/> |
| cpuReset |
false |
| cpuID |
0 |
| clockFrequency |
50000000 |
| breakSlave |
cpu.jtag_debug_module |
| breakOffset |
32 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |