module delay ( input a, clk, output reg y ); reg [19:0] s; always @ (posedge clk) begin s[0] <= a; s[1] <= s[0]; s[2] <= s[1]; s[3] <= s[2]; s[4] <= s[3]; s[5] <= s[4]; s[6] <= s[5]; s[7] <= s[6]; s[8] <= s[7]; s[9] <= s[8]; s[10] <= s[9]; s[11] <= s[10]; s[12] <= s[11]; s[13] <= s[12]; s[14] <= s[13]; s[15] <= s[14]; s[16] <= s[15]; s[17] <= s[16]; s[18] <= s[17]; s[19] <= s[18]; y <= s[19]; end endmodule