module edges ( input clk, input [29:0] x00, x01, x02, x10, x11, x12, x20, x21, x22, output reg [29:0] p ); wire [15:0] R00 = x00[29:20]; wire [15:0] R01 = x01[29:20]; wire [15:0] R02 = x02[29:20]; wire [15:0] R10 = x10[29:20]; wire [15:0] R11 = x11[29:20]; wire [15:0] R12 = x12[29:20]; wire [15:0] R20 = x20[29:20]; wire [15:0] R21 = x21[29:20]; wire [15:0] R22 = x22[29:20]; wire [15:0] G00 = x00[19:10]; wire [15:0] G01 = x01[19:10]; wire [15:0] G02 = x02[19:10]; wire [15:0] G10 = x10[19:10]; wire [15:0] G11 = x11[19:10]; wire [15:0] G12 = x12[19:10]; wire [15:0] G20 = x20[19:10]; wire [15:0] G21 = x21[19:10]; wire [15:0] G22 = x22[19:10]; wire [15:0] B00 = x00[9:0]; wire [15:0] B01 = x01[9:0]; wire [15:0] B02 = x02[9:0]; wire [15:0] B10 = x10[9:0]; wire [15:0] B11 = x11[9:0]; wire [15:0] B12 = x12[9:0]; wire [15:0] B20 = x20[9:0]; wire [15:0] B21 = x21[9:0]; wire [15:0] B22 = x22[9:0]; // wire [15:0] M00 = R00 + G00 + B00; // wire [15:0] M01 = R01 + G01 + B01; // wire [15:0] M02 = R02 + G02 + B02; // wire [15:0] M10 = R10 + G10 + B10; // wire [15:0] M11 = R11 + G11 + B11; // wire [15:0] M12 = R12 + G12 + B12; // wire [15:0] M20 = R20 + G20 + B20; // wire [15:0] M21 = R21 + G21 + B21; // wire [15:0] M22 = R22 + G22 + B22; // reg signed [16:0] M; // wire [33:0] M2; // squarer s (M, M2); wire signed [16:0] R = R00 + R01 + R02 + R10 + R12 + R20 + R21 + R22 - {R11,3'b0}; wire signed [16:0] G = G00 + G01 + G02 + G10 + G12 + G20 + G21 + G22 - {G11,3'b0}; wire signed [16:0] B = B00 + B01 + B02 + B10 + B12 + B20 + B21 + B22 - {B11,3'b0}; always @ (posedge clk) begin // M <= {M11,3'b0} - M00 - M01 - M02 - M10 - M12 - M20 - M21 - M22; // p <= M2 > {thres,16'b0} ? ~30'b0 : 30'b0; // if (M2 > {1'b1,20'b0}) p <= {10'b0,10'd1023,10'b0}; // else if (M2 > {1'b1,19'b0}) p <= {10'b0,10'd511,10'b0}; // else if (M2 > {1'b1,18'b0}) p <= {10'b0,10'b0,10'd1023}; // else if (M2 > {1'b1,17'b0}) p <= {10'b0,10'b0,10'd511}; // else if (M2 > {1'b1,16'b0}) p <= {10'b0,10'b0,10'b0}; p <= {R[12:3], G[12:3], B[12:3]}; end endmodule