module Example_4_Video_In ( // Inputs CLOCK_50, TD_CLK27, KEY, SW, // Video In TD_DATA, TD_HS, TD_VS, /*****************************************************************************/ // Bidirectionals // Memory (SRAM) SRAM_DQ, // AV Config I2C_SDAT, /*****************************************************************************/ // Outputs TD_RESET_N, // Memory (SRAM) SRAM_ADDR, SRAM_CE_N, SRAM_WE_N, SRAM_OE_N, SRAM_UB_N, SRAM_LB_N, // VGA VGA_CLK, VGA_HS, VGA_VS, VGA_BLANK_N, VGA_SYNC_N, VGA_R, VGA_G, VGA_B, // AV Config I2C_SCLK, // LEDS LEDR, LEDG, GPIO ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input CLOCK_50; input TD_CLK27; input [ 3: 0] KEY; input [17: 0] SW; // Video In input [ 7: 0] TD_DATA; input TD_HS; input TD_VS; // Bidirectionals // Memory (SRAM) inout [15: 0] SRAM_DQ; // Bidirectionals inout [35: 0] GPIO; // AV Config inout I2C_SDAT; // Outputs output TD_RESET_N; // Memory (SRAM) output [19: 0] SRAM_ADDR; output SRAM_CE_N; output SRAM_WE_N; output SRAM_OE_N; output SRAM_UB_N; output SRAM_LB_N; // VGA output VGA_CLK; output VGA_HS; output VGA_VS; output VGA_BLANK_N; output VGA_SYNC_N; output [ 7: 0] VGA_R; output [ 7: 0] VGA_G; output [ 7: 0] VGA_B; // AV Config output I2C_SCLK; // LEDR output [17:0] LEDR; output [8:0] LEDG; /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers // State Machine Registers //Memory output to VGA wire [9:0] mVGA_R; //10 bit Red Color wire [9:0] mVGA_G; //10 bit Green Color wire [9:0] mVGA_B; //10 bit Blue Color wire [19:0] mVGA_ADDR; //VGA Pixel Address wire [9:0] Coord_X, Coord_Y; //VGA Pixel Coordinates wire DLY_RST; //Reset delay line wire [7:0] VGA_data; /***************************************************************************** * Internal Wires and Registers Declarations * *****************************************************************************/ // this is coming from NIOS wire [7:0] CUBE_MOVE; wire stateClock/* synthesis keep preserve */; /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ reg [9:0] cubeAddress/* synthesis keep preserve */; wire [3:0] cubeData/* synthesis keep preserve */; wire cubeClock/* synthesis keep preserve */; wire cubeReset/* synthesis keep preserve */; wire cubeWE/* synthesis keep preserve */; wire finished/* synthesis keep preserve */; wire readClock/* synthesis keep preserve */; wire [7:0] readData/* synthesis keep preserve */; reg [9:0] readAddress/* synthesis keep preserve */; //assign readClock = CUBE_MOVE[4]; assign readClock = stateClock; assign cubeData = CUBE_MOVE[3:0]; assign cubeClock = CUBE_MOVE[4]; assign cubeReset = CUBE_MOVE[5]; assign cubeWE = CUBE_MOVE[6]; assign finished = CUBE_MOVE[7]; CubeMemory mem( .data(cubeData), .wrclock(cubeClock), .wraddress(cubeAddress), .wren(cubeWE), .rdaddress(readAddress), .rdclock(stateClock), .q(readData) ); always@(posedge cubeReset or negedge cubeClock) begin if(cubeReset) begin cubeAddress <= 0; end else begin if(SW[0]) begin cubeAddress <= 0; end else begin cubeAddress <= cubeAddress + 1; end end end //assign LEDG = readData; //assign LEDR[7:0] = readAddress; //assign LEDR[17:8] = cubeAddress; /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ //Servo stuff reg [7:0] servos; assign GPIO[11] = servos[0]; assign GPIO[13] = servos[1]; assign GPIO[15] = servos[2]; assign GPIO[17] = servos[3]; assign GPIO[21] = servos[4]; assign GPIO[23] = servos[5]; reg [15:0] pwmCounter; reg [3:0] state/* synthesis keep preserve */; reg [3:0] returnState/* synthesis keep preserve */; parameter startup = 0, idle = 8, move = 1, moveDelay = 2, startMove = 3, determineFace = 4, determineRotation = 5, determineRotateCommand = 6, moveFinished = 7; parameter cOpen = 0, cClosed = 1, cPartialOpen = 3, negNinety = 3, zero = 4, posNinety = 5; //Moves, servo num, sequence wire [3:0] moves[9:0][5:0][8:0]/* synthesis keep preserve */; wire [15:0] positions[5:0][5:0]/* synthesis keep preserve */; reg [15:0] currentPos[5:0]/* synthesis keep preserve */; //Number of moves for each command wire [4:0] numMoves[9:0]/* synthesis keep preserve */; reg [4:0] currentMove/* synthesis keep preserve */; reg [3:0] currentCommand/* synthesis keep preserve */; `include "PerformMove.h" `include "Positions.h" `include "MoveSequences.h" integer servoNum; reg [31:0] currentDelay; reg servoEnable; parameter delay = 2550000; //115 //Handle the PWM positions always@(posedge stateClock) begin pwmCounter <= pwmCounter + 1; for(servoNum = 0; servoNum < 6; servoNum = servoNum + 1) begin if(pwmCounter > currentPos[servoNum]) begin servos[servoNum] <= 0; end else begin servos[servoNum] <= 1; end end end /***************************************************************************** * Sequential Logic * *****************************************************************************/ /***************************************************************************** * Combinational Logic * *****************************************************************************/ // Output Assignments assign TD_RESET_N = 1'b1; /***************************************************************************** * Internal Modules * *****************************************************************************/ Reset_Delay r0 (.iCLK(CLOCK_50),.oRESET(DLY_RST) ); StatePLL p1 (.areset(~DLY_RST),.inclk0(CLOCK_50),.c1(stateClock)); Video_System Video_System ( // 1) global signals: .clk (CLOCK_50), .reset_n (KEY[0]), // the_AV_Config .I2C_SDAT_to_and_from_the_AV_Config (I2C_SDAT), .I2C_SCLK_from_the_AV_Config (I2C_SCLK), // the_Pixel_Buffer .SRAM_DQ_to_and_from_the_Pixel_Buffer (SRAM_DQ), .SRAM_ADDR_from_the_Pixel_Buffer (SRAM_ADDR), .SRAM_LB_N_from_the_Pixel_Buffer (SRAM_LB_N), .SRAM_UB_N_from_the_Pixel_Buffer (SRAM_UB_N), .SRAM_CE_N_from_the_Pixel_Buffer (SRAM_CE_N), .SRAM_OE_N_from_the_Pixel_Buffer (SRAM_OE_N), .SRAM_WE_N_from_the_Pixel_Buffer (SRAM_WE_N), // the_Video_In_Decoder .TD_CLK27_to_the_Video_In_Decoder (TD_CLK27), .TD_DATA_to_the_Video_In_Decoder (TD_DATA), .TD_HS_to_the_Video_In_Decoder (TD_HS), .TD_RESET_from_the_Video_In_Decoder (), .TD_VS_to_the_Video_In_Decoder (TD_VS), // the_VGA_Controller .VGA_CLK_from_the_VGA_Controller (VGA_CLK), .VGA_HS_from_the_VGA_Controller (VGA_HS), .VGA_VS_from_the_VGA_Controller (VGA_VS), .VGA_BLANK_from_the_VGA_Controller (VGA_BLANK_N), .VGA_SYNC_from_the_VGA_Controller (VGA_SYNC_N), .VGA_R_from_the_VGA_Controller (VGA_R), .VGA_G_from_the_VGA_Controller (VGA_G), .VGA_B_from_the_VGA_Controller (VGA_B), // LEDs .LEDR_from_the_LED_RED (LEDR), .LEDG_from_the_LED_GREEN (LEDG), //Nios to FPGA interface .out_port_from_the_CUBE_MOVE (CUBE_MOVE), .SW_to_the_SWITCHES (SW), .in_port_to_the_Servos_To_NIOS (finishedMoves) ); endmodule