Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
fm 64 0 0 0 2 0 0 0 0 0 0 0 0
u11|altshift_taps_component|auto_generated|cntr1|cmpr5 20 0 0 0 1 0 0 0 0 0 0 0 0
u11|altshift_taps_component|auto_generated|cntr1 2 0 0 0 10 0 0 0 0 0 0 0 0
u11|altshift_taps_component|auto_generated|altsyncram2 39 1 0 1 16 1 1 1 0 0 0 0 0
u11|altshift_taps_component|auto_generated 18 0 0 0 32 0 0 0 0 0 0 0 0
u11 18 0 0 0 16 0 0 0 0 0 0 0 0
u10|altshift_taps_component|auto_generated|cntr1|cmpr5 20 0 0 0 1 0 0 0 0 0 0 0 0
u10|altshift_taps_component|auto_generated|cntr1 2 0 0 0 10 0 0 0 0 0 0 0 0
u10|altshift_taps_component|auto_generated|altsyncram2 39 1 0 1 16 1 1 1 0 0 0 0 0
u10|altshift_taps_component|auto_generated 18 0 0 0 32 0 0 0 0 0 0 0 0
u10 18 0 0 0 16 0 0 0 0 0 0 0 0
processor|niosII_reset_vga_clk_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
processor|niosII_reset_clk_0_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
processor|niosII_reset_sys_clk_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
processor|the_niosII_clock_1|endofpacket_bit_pipe 5 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1|master_FSM 5 0 0 0 4 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1|write_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1|read_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1|slave_FSM 6 0 0 0 3 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1|write_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1|read_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1 82 1 0 1 78 1 1 1 0 0 0 0 0
processor|the_niosII_clock_1_out 81 0 40 0 38 0 0 0 0 0 0 0 0
processor|the_niosII_clock_1_in 95 1 2 1 84 1 1 1 0 0 0 0 0
processor|the_niosII_clock_0|endofpacket_bit_pipe 5 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0|master_FSM 5 0 0 0 4 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0|write_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0|read_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0|slave_FSM 6 0 0 0 3 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0|write_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0|read_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0 26 1 0 1 22 1 1 1 0 0 0 0 0
processor|the_niosII_clock_0_out 26 0 11 0 11 0 0 0 0 0 0 0 0
processor|the_niosII_clock_0_in 50 1 1 1 29 1 1 1 0 0 0 0 0
processor|the_VGA_Controller|VGA_Timing 36 0 1 0 47 0 0 0 0 0 0 0 0
processor|the_VGA_Controller 35 0 1 0 36 0 0 0 0 0 0 0 0
processor|the_VGA_Controller_avalon_vga_sink 36 0 1 0 35 0 0 0 0 0 0 0 0
processor|the_Pixel_RGB_Resampler 14 0 0 0 34 0 0 0 0 0 0 0 0
processor|the_Pixel_RGB_Resampler_avalon_rgb_source 36 0 35 0 1 0 0 0 0 0 0 0 0
processor|the_Pixel_RGB_Resampler_avalon_rgb_sink 14 0 1 0 13 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated|dpfifo|wr_ptr 3 0 0 0 7 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated|dpfifo|usedw_counter 4 0 0 0 7 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated|dpfifo|rd_ptr_msb 3 0 0 0 6 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated|dpfifo|three_comparison 14 7 0 7 1 7 7 7 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated|dpfifo|almost_full_comparer 14 7 0 7 1 7 7 7 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated|dpfifo|FIFOram 26 0 0 0 10 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated|dpfifo 14 0 0 0 19 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA|Image_Buffer|auto_generated 14 0 0 0 14 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA 53 0 0 0 77 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA_avalon_pixel_source 14 0 13 0 1 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer_DMA_avalon_pixel_dma_master|selecto_nrdv_Pixel_Buffer_DMA_avalon_pixel_dma_master_1_Pixel_Buffer_avalon_sram_slave_fifo 7 2 0 2 3 2 2 2 0 0 0 0 0
processor|the_Pixel_Buffer_DMA_avalon_pixel_dma_master 57 13 15 13 44 13 13 13 0 0 0 0 0
processor|the_Pixel_Buffer_DMA_avalon_control_slave 93 0 2 0 78 0 0 0 0 0 0 0 0
processor|the_Pixel_Buffer 40 0 0 0 40 0 0 0 16 0 0 0 0
processor|the_Pixel_Buffer_avalon_sram_slave|rdv_fifo_for_Pixel_Buffer_DMA_avalon_pixel_dma_master_to_Pixel_Buffer_avalon_sram_slave 7 2 0 2 2 2 2 2 0 0 0 0 0
processor|the_Pixel_Buffer_avalon_sram_slave|rdv_fifo_for_CPU_data_master_to_Pixel_Buffer_avalon_sram_slave 7 2 0 2 2 2 2 2 0 0 0 0 0
processor|the_Pixel_Buffer_avalon_sram_slave 100 0 4 0 68 0 0 0 0 0 0 0 0
processor|the_PIO_Valid 39 0 32 0 32 0 0 0 0 0 0 0 0
processor|the_PIO_Valid_s1 89 1 2 1 74 1 1 1 0 0 0 0 0
processor|the_PIO_Transmit_Data 12 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_PIO_Transmit_Data_s1 56 1 2 1 40 1 1 1 0 0 0 0 0
processor|the_PIO_Received_Data 12 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_PIO_Received_Data_s1 56 1 2 1 40 1 1 1 0 0 0 0 0
processor|the_PIO_Ready_Signal 5 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_PIO_Ready_Signal_s1 56 1 2 1 40 1 1 1 0 0 0 0 0
processor|the_PIO_Count 36 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_PIO_Count_s1 42 1 4 1 40 1 1 1 0 0 0 0 0
processor|the_Onchip_Memory|the_altsyncram|auto_generated 51 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_Onchip_Memory 53 0 1 0 32 0 0 0 0 0 0 0 0
processor|the_Onchip_Memory_s1 114 1 4 1 94 1 1 1 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrfull_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrfull_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdemp_eq_comp_msb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdemp_eq_comp_lsb_mux 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrfull_eq_comp_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrfull_eq_comp_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrfull_eq_comp1_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrfull_eq_comp1_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdempty_eq_comp_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdempty_eq_comp_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdempty_eq_comp1_msb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdempty_eq_comp1_lsb 8 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|ws_dgrp|dffpipe20 9 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|ws_dgrp 9 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|ws_bwp 9 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|ws_brp 9 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rs_dgwp|dffpipe16 9 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rs_dgwp 9 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdaclr 2 1 0 1 1 1 1 1 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|fifo_ram 50 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrptr_gp 2 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrptr_g1p 2 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|rdptr_g1p 3 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|ws_dgrp_gray2bin 8 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated|wrptr_g_gray2bin 8 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO|Data_FIFO|auto_generated 36 0 0 0 40 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO 36 0 0 0 34 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO_avalon_dc_buffer_source 36 0 35 0 1 0 0 0 0 0 0 0 0
processor|the_Dual_Clock_FIFO_avalon_dc_buffer_sink 36 0 2 0 34 0 0 0 0 0 0 0 0
processor|the_Clock_Signals 2 0 0 0 10 0 0 0 0 0 0 0 0
processor|the_Clock_Signals_avalon_clocks_slave 13 0 0 0 14 0 0 0 0 0 0 0 0
processor|the_Char_LCD_16x2|Char_LCD_Init 4 0 0 0 11 0 0 0 0 0 0 0 0
processor|the_Char_LCD_16x2|Char_LCD_Comm 15 2 0 2 14 2 2 2 8 0 0 0 0
processor|the_Char_LCD_16x2 14 0 1 0 14 0 0 0 8 0 0 0 0
processor|the_Char_LCD_16x2_avalon_lcd_slave 49 1 1 1 28 1 1 1 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Character_Rom|character_data_rom|auto_generated|mux2 3 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Character_Rom|character_data_rom|auto_generated 15 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Character_Rom 15 0 0 0 1 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Char_Buffer_Memory|auto_generated|altsyncram1|mux6 34 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Char_Buffer_Memory|auto_generated|altsyncram1|mux5 34 0 0 0 8 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Char_Buffer_Memory|auto_generated|altsyncram1|decode_a 3 1 0 1 4 1 1 1 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Char_Buffer_Memory|auto_generated|altsyncram1|decode4 3 0 0 0 4 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Char_Buffer_Memory|auto_generated|altsyncram1|decode3 3 0 0 0 4 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Char_Buffer_Memory|auto_generated|altsyncram1 49 2 0 2 16 2 2 2 0 0 0 0 0
processor|the_Char_Buffer_with_DMA|Char_Buffer_Memory|auto_generated 47 0 0 0 16 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA 68 1 1 1 84 1 1 1 0 0 0 0 0
processor|the_Char_Buffer_with_DMA_avalon_char_source 46 0 45 0 1 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA_avalon_char_control_slave 93 0 2 0 79 0 0 0 0 0 0 0 0
processor|the_Char_Buffer_with_DMA_avalon_char_buffer_slave 49 0 2 0 41 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_jtag_debug_module_wrapper|the_CPU_jtag_debug_module_sysclk 43 0 0 0 51 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_jtag_debug_module_wrapper|the_CPU_jtag_debug_module_tck 130 0 1 0 43 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_jtag_debug_module_wrapper 123 0 0 0 53 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_im|CPU_traceram_lpm_dram_bdp_component|the_altsyncram|auto_generated|altsyncram1 94 2 0 2 72 2 2 2 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_im|CPU_traceram_lpm_dram_bdp_component|the_altsyncram|auto_generated 92 0 0 0 72 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_im|CPU_traceram_lpm_dram_bdp_component 92 2 0 2 72 2 2 2 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_im 97 36 17 36 48 36 36 36 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_pib 39 20 38 20 19 20 20 20 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_fifo|the_CPU_oci_test_bench 36 0 36 0 0 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_fifo|CPU_nios2_oci_fifocount_inc_fifocount 5 0 0 0 5 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_fifo|CPU_nios2_oci_fifowp_inc_fifowp 4 2 0 2 4 2 2 2 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_fifo|CPU_nios2_oci_compute_tm_count_tm_count 3 0 0 0 2 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_fifo 151 0 65 0 36 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_dtrace|CPU_nios2_oci_trc_ctrl_td_mode 9 0 6 0 4 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_dtrace 105 0 94 0 72 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_itrace 25 17 23 17 87 17 17 17 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_dbrk 90 0 0 0 94 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_xbrk 56 5 53 5 6 5 5 5 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_break 52 36 6 36 71 36 36 36 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_avalon_reg 49 0 29 0 68 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_ocimem|CPU_ociram_lpm_dram_bdp_component|the_altsyncram|auto_generated|altsyncram1 92 2 0 2 64 2 2 2 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_ocimem|CPU_ociram_lpm_dram_bdp_component|the_altsyncram|auto_generated 90 0 0 0 64 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_ocimem|CPU_ociram_lpm_dram_bdp_component 90 2 0 2 64 2 2 2 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_ocimem 93 0 6 0 64 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci|the_CPU_nios2_oci_debug 50 1 30 1 7 1 1 1 0 0 0 0 0
processor|the_CPU|the_CPU_nios2_oci 162 0 0 0 68 0 0 0 0 0 0 0 0
processor|the_CPU|CPU_register_bank_b|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_CPU|CPU_register_bank_b 44 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_CPU|CPU_register_bank_a|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_CPU|CPU_register_bank_a 44 0 0 0 32 0 0 0 0 0 0 0 0
processor|the_CPU|the_CPU_test_bench 467 3 430 3 34 3 3 3 0 0 0 0 0
processor|the_CPU 149 32 0 32 113 32 32 32 0 0 0 0 0
processor|the_CPU_instruction_master 97 4 8 4 53 4 4 4 0 0 0 0 0
processor|the_CPU_data_master 463 0 32 0 80 0 0 0 0 0 0 0 0
processor|the_CPU_jtag_debug_module 116 2 4 2 92 2 2 2 0 0 0 0 0
processor|the_Alpha_Blender|alpha_blender 70 0 9 0 30 0 0 0 0 0 0 0 0
processor|the_Alpha_Blender 79 0 2 0 35 0 0 0 0 0 0 0 0
processor|the_Alpha_Blender_avalon_blended_source 36 0 35 0 1 0 0 0 0 0 0 0 0
processor|the_Alpha_Blender_avalon_foreground_sink 46 0 1 0 45 0 0 0 0 0 0 0 0
processor|the_Alpha_Blender_avalon_background_sink 36 0 2 0 34 0 0 0 0 0 0 0 0
processor 52 0 0 0 64 0 0 0 24 0 0 0 0
u9 32 21 0 21 80 21 21 21 0 0 0 0 0
mux 71 0 0 0 35 0 0 0 0 0 0 0 0
u18|RS232_In_Counter 3 0 0 0 2 0 0 0 0 0 0 0 0
u18 4 1 0 1 10 1 1 1 0 0 0 0 0
u17|Out_Counter 3 0 0 0 2 0 0 0 0 0 0 0 0
u17 11 0 0 0 2 0 0 0 0 0 0 0 0
trig 2 0 0 0 1 0 0 0 0 0 0 0 0
u100|ram3|altsyncram_component|auto_generated 32 0 0 0 10 0 0 0 0 0 0 0 0
u100|ram3 32 0 0 0 10 0 0 0 0 0 0 0 0
u100|ram2|altsyncram_component|auto_generated 32 0 0 0 10 0 0 0 0 0 0 0 0
u100|ram2 32 0 0 0 10 0 0 0 0 0 0 0 0
u100|ram1|altsyncram_component|auto_generated 32 0 0 0 10 0 0 0 0 0 0 0 0
u100|ram1 32 0 0 0 10 0 0 0 0 0 0 0 0
u100 33 0 0 0 30 0 0 0 0 0 0 0 0
u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult3|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult3 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult2|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult2 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult1|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u2|ALTMULT_ADD_component|auto_generated|ded_mult1 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u2|ALTMULT_ADD_component|auto_generated 77 0 0 0 27 0 0 0 0 0 0 0 0
u8|u2 77 51 0 51 27 51 51 51 0 0 0 0 0
u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult3|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult3 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult2|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult2 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult1|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u1|ALTMULT_ADD_component|auto_generated|ded_mult1 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u1|ALTMULT_ADD_component|auto_generated 77 0 0 0 27 0 0 0 0 0 0 0 0
u8|u1 77 51 0 51 27 51 51 51 0 0 0 0 0
u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult3|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult3 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult2|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult2 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult1|pre_result 25 0 0 0 25 0 0 0 0 0 0 0 0
u8|u0|ALTMULT_ADD_component|auto_generated|ded_mult1 37 9 0 9 25 9 9 9 0 0 0 0 0
u8|u0|ALTMULT_ADD_component|auto_generated 77 0 0 0 27 0 0 0 0 0 0 0 0
u8|u0 77 51 0 51 27 51 51 51 0 0 0 0 0
u8 27 0 0 0 31 0 0 0 0 0 0 0 0
u7 28 0 9 0 24 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe22 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|ws_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|ws_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe18 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rs_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rs_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rdaclr 3 1 0 1 1 1 1 1 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|fifo_ram|altsyncram14 58 17 0 17 16 17 17 17 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|fifo_ram 40 0 0 0 16 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|wrptr_gp 3 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 0 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
u6|read_fifo2|dcfifo_component|auto_generated 21 0 0 0 36 0 0 0 0 0 0 0 0
u6|read_fifo2 21 0 0 0 35 0 0 0 0 0 0 0 0
u6|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
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