niosII

2015.05.12.04:06:15 Datasheet
Overview
  clk_0  niosII
  clk_1 
   PIO_Ready_Signal
 in_port  
 in_port  
 in_port  
 in_port  
 in_port  
Processor
   CPU Nios II 11.0
All Components
   CPU altera_nios2 11.0
   Onchip_Memory altera_avalon_onchip_memory2 11.0
   Clock_Signals altera_up_avalon_clocks 11.0
   Char_Buffer_with_DMA altera_up_avalon_video_character_buffer_with_dma 11.0
   Pixel_Buffer altera_up_avalon_sram 11.0
   Pixel_Buffer_DMA altera_up_avalon_video_pixel_buffer_dma 11.0
   Char_LCD_16x2 altera_up_avalon_character_lcd 11.0
   PIO_Ready_Signal altera_avalon_pio 11.0
   PIO_Transmit_Data altera_avalon_pio 11.0
   PIO_Received_Data altera_avalon_pio 11.0
   PIO_Valid altera_avalon_pio 11.0
   PIO_Count altera_avalon_pio 11.0
Memory Map
CPU Pixel_Buffer_DMA
 instruction_master  data_master  avalon_pixel_dma_master
  CPU
jtag_debug_module  0x0008a800 0x0008a800
  Onchip_Memory
s1  0x00084000 0x00084000
  Clock_Signals
avalon_clocks_slave  0x0008b068
  Char_Buffer_with_DMA
avalon_char_control_slave  0x0008b060
avalon_char_buffer_slave  0x00088000
  Pixel_Buffer
avalon_sram_slave  0x00000000 0x00000000
  Pixel_Buffer_DMA
avalon_control_slave  0x0008b000
  Char_LCD_16x2
avalon_lcd_slave  0x0008b06a
  PIO_Ready_Signal
s1  0x0008b020
  PIO_Transmit_Data
s1  0x0008b030
  PIO_Received_Data
s1  0x0008b040
  PIO_Valid
s1  0x0008b050
  PIO_Count
s1  0x0008b010

clk_0

clock_source v11.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

CPU

altera_nios2 v11.0
Clock_Signals sys_clk   CPU
  clk
instruction_master   Onchip_Memory
  s1
data_master  
  s1
data_master   Clock_Signals
  avalon_clocks_slave
data_master   Char_Buffer_with_DMA
  avalon_char_control_slave
data_master  
  avalon_char_buffer_slave
data_master   Pixel_Buffer
  avalon_sram_slave
data_master   Pixel_Buffer_DMA
  avalon_control_slave
data_master   Char_LCD_16x2
  avalon_lcd_slave
data_master   PIO_Ready_Signal
  s1
data_master   PIO_Transmit_Data
  s1
data_master   PIO_Received_Data
  s1
data_master   PIO_Valid
  s1
data_master   PIO_Count
  s1


Parameters

userDefinedSettings
tightlyCoupledInstructionMaster3MapParam
tightlyCoupledInstructionMaster3AddrWidth 1
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledDataMaster3MapParam
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster0AddrWidth 1
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave Onchip_Memory.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 0
instSlaveMapParam <address-map><slave name='Onchip_Memory.s1' start='0x84000' end='0x88000' /><slave name='CPU.jtag_debug_module' start='0x8A800' end='0x8B000' /></address-map>
instAddrWidth 20
impl Tiny
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave Onchip_Memory.s1
exceptionOffset 32
deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName Cyclone II
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
dataSlaveMapParam <address-map><slave name='Pixel_Buffer.avalon_sram_slave' start='0x0' end='0x80000' /><slave name='Onchip_Memory.s1' start='0x84000' end='0x88000' /><slave name='Char_Buffer_with_DMA.avalon_char_buffer_slave' start='0x88000' end='0x8A000' /><slave name='CPU.jtag_debug_module' start='0x8A800' end='0x8B000' /><slave name='Pixel_Buffer_DMA.avalon_control_slave' start='0x8B000' end='0x8B010' /><slave name='PIO_Count.s1' start='0x8B010' end='0x8B020' /><slave name='PIO_Ready_Signal.s1' start='0x8B020' end='0x8B030' /><slave name='PIO_Transmit_Data.s1' start='0x8B030' end='0x8B040' /><slave name='PIO_Received_Data.s1' start='0x8B040' end='0x8B050' /><slave name='PIO_Valid.s1' start='0x8B050' end='0x8B060' /><slave name='Char_Buffer_with_DMA.avalon_char_control_slave' start='0x8B060' end='0x8B068' /><slave name='Clock_Signals.avalon_clocks_slave' start='0x8B068' end='0x8B06A' /><slave name='Char_LCD_16x2.avalon_lcd_slave' start='0x8B06A' end='0x8B06C' /></address-map>
dataAddrWidth 20
customInstSlavesSystemInfo <info/>
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave CPU.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "tiny"
BIG_ENDIAN 0
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x84020
RESET_ADDR 0x84000
BREAK_ADDR 0x8a820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_MULTIPLY_PRESENT 0
HARDWARE_MULX_PRESENT 0
HARDWARE_DIVIDE_PRESENT 0
INST_ADDR_WIDTH 20
DATA_ADDR_WIDTH 20

Onchip_Memory

altera_avalon_onchip_memory2 v11.0
CPU instruction_master   Onchip_Memory
  s1
data_master  
  s1
Clock_Signals sys_clk  
  clk1


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName Onchip_Memory
blockType AUTO
dataWidth 32
deviceFamily Cyclone II
dualPort false
initMemContent true
initializationFileName Onchip_Memory
instanceID NONE
memorySize 16384
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "Onchip_Memory"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SINGLE_CLOCK_OP 0
SIZE_VALUE 16384u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

Clock_Signals

altera_up_avalon_clocks v11.0
CPU data_master   Clock_Signals
  avalon_clocks_slave
clk_0 clk  
  clk_in_primary
sys_clk   Onchip_Memory
  clk1
sys_clk   CPU
  clk
sys_clk   Char_Buffer_with_DMA
  clock_reset
sys_clk   Pixel_Buffer
  clock_reset
sys_clk   Pixel_RGB_Resampler
  clock_reset
sys_clk   Alpha_Blender
  clock_reset
sys_clk   Dual_Clock_FIFO
  clock_stream_in
vga_clk  
  clock_stream_out
vga_clk   VGA_Controller
  clock_reset
sys_clk   Char_LCD_16x2
  clock_reset
sys_clk   PIO_Ready_Signal
  clk
sys_clk   PIO_Transmit_Data
  clk
sys_clk   PIO_Received_Data
  clk
sys_clk   PIO_Valid
  clk
sys_clk   Pixel_Buffer_DMA
  clock_reset


Parameters

board DE2
sys_clk_freq 50
sdram_clk false
vga_clk true
audio_clk false
audio_clk_freq 12.288
AUTO_CLK_IN_PRIMARY_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Char_Buffer_with_DMA

altera_up_avalon_video_character_buffer_with_dma v11.0
CPU data_master   Char_Buffer_with_DMA
  avalon_char_control_slave
data_master  
  avalon_char_buffer_slave
Clock_Signals sys_clk  
  clock_reset
avalon_char_source   Alpha_Blender
  avalon_foreground_sink


Parameters

vga_device On-board VGA DAC
enable_transparency true
color_bits 1-bit
resolution 80 x 60
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Pixel_Buffer

altera_up_avalon_sram v11.0
CPU data_master   Pixel_Buffer
  avalon_sram_slave
Pixel_Buffer_DMA avalon_pixel_dma_master  
  avalon_sram_slave
Clock_Signals sys_clk  
  clock_reset


Parameters

board DE2
pixel_buffer true
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Pixel_Buffer_DMA

altera_up_avalon_video_pixel_buffer_dma v11.0
CPU data_master   Pixel_Buffer_DMA
  avalon_control_slave
Clock_Signals sys_clk  
  clock_reset
avalon_pixel_dma_master   Pixel_Buffer
  avalon_sram_slave
avalon_pixel_source   Pixel_RGB_Resampler
  avalon_rgb_sink


Parameters

addr_mode X-Y
start_address 0
back_start_address 0
image_width 640
image_height 480
color_space 8-bit RGB
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Pixel_RGB_Resampler

altera_up_avalon_video_rgb_resampler v11.0
Pixel_Buffer_DMA avalon_pixel_source   Pixel_RGB_Resampler
  avalon_rgb_sink
Clock_Signals sys_clk  
  clock_reset
avalon_rgb_source   Alpha_Blender
  avalon_background_sink


Parameters

input_type 8-bit RGB
output_type 30-bit RGB
alpha 1023
input_bits 8
input_planes 1
output_bits 10
output_planes 3
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Alpha_Blender

altera_up_avalon_video_alpha_blender v11.0
Char_Buffer_with_DMA avalon_char_source   Alpha_Blender
  avalon_foreground_sink
Pixel_RGB_Resampler avalon_rgb_source  
  avalon_background_sink
Clock_Signals sys_clk  
  clock_reset
avalon_blended_source   Dual_Clock_FIFO
  avalon_dc_buffer_sink


Parameters

mode Simple
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

Dual_Clock_FIFO

altera_up_avalon_video_dual_clock_buffer v11.0
Alpha_Blender avalon_blended_source   Dual_Clock_FIFO
  avalon_dc_buffer_sink
Clock_Signals sys_clk  
  clock_stream_in
vga_clk  
  clock_stream_out
avalon_dc_buffer_source   VGA_Controller
  avalon_vga_sink


Parameters

color_bits 10
color_planes 3
AUTO_CLOCK_STREAM_IN_CLOCK_RATE 50000000
AUTO_CLOCK_STREAM_OUT_CLOCK_RATE 25000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

VGA_Controller

altera_up_avalon_video_vga_controller v11.0
Dual_Clock_FIFO avalon_dc_buffer_source   VGA_Controller
  avalon_vga_sink
Clock_Signals vga_clk  
  clock_reset


Parameters

board DE2
device VGA Connector
underflow_flag false
AUTO_CLOCK_RESET_CLOCK_RATE 25000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

clk_1

clock_source v11.0


Parameters

clockFrequency 27000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

Char_LCD_16x2

altera_up_avalon_character_lcd v11.0
CPU data_master   Char_LCD_16x2
  avalon_lcd_slave
Clock_Signals sys_clk  
  clock_reset


Parameters

cursor Normal
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

PIO_Ready_Signal

altera_avalon_pio v11.0
CPU data_master   PIO_Ready_Signal
  s1
Clock_Signals sys_clk  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

PIO_Transmit_Data

altera_avalon_pio v11.0
CPU data_master   PIO_Transmit_Data
  s1
Clock_Signals sys_clk  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

PIO_Received_Data

altera_avalon_pio v11.0
CPU data_master   PIO_Received_Data
  s1
Clock_Signals sys_clk  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

PIO_Valid

altera_avalon_pio v11.0
CPU data_master   PIO_Valid
  s1
Clock_Signals sys_clk  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 50000000
direction Input
edgeType FALLING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "NONE"
FREQ 50000000u

PIO_Count

altera_avalon_pio v11.0
clk_0 clk   PIO_Count
  clk
CPU data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 32
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u
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