| 1 | // DE2_115_Media_Computer.v
|
| 2 | // Authors: Ryan Land, Gautham Ponnu
|
| 3 | // ECE 5760 - Final Project
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| 4 | // May 16, 2016
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| 5 |
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| 6 | // TOP LEVEL MODULE
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| 7 | module DE2_115_Media_Computer (
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| 8 |
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| 9 |
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| 10 | // Inputs
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| 11 | CLOCK_50,
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| 12 | TD_CLK27,
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| 13 | KEY,
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| 14 | SW,
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| 15 |
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| 16 | // Communication
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| 17 | UART_RXD,
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| 18 |
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| 19 | // Audio
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| 20 | AUD_ADCDAT,
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| 21 |
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| 22 | // IrDA
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| 23 | IRDA_RXD,
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| 24 |
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| 25 | // Video In
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| 26 | TD_DATA,
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| 27 | TD_HS,
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| 28 | TD_VS,
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| 29 |
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| 30 | // USB
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| 31 | OTG_INT,
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| 32 |
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| 33 | /*****************************************************************************/
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| 34 | // Bidirectionals
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| 35 | GPIO,
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| 36 |
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| 37 | // Memory (SRAM)
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| 38 | SRAM_DQ,
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| 39 |
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| 40 | // Memory (SDRAM)
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| 41 | DRAM_DQ,
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| 42 |
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| 43 | // PS2 Port
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| 44 | PS2_KBCLK,
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| 45 | PS2_KBDAT,
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| 46 | PS2_MSCLK,
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| 47 | PS2_MSDAT,
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| 48 |
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| 49 | // Audio
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| 50 | AUD_BCLK,
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| 51 | AUD_ADCLRCK,
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| 52 | AUD_DACLRCK,
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| 53 |
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| 54 | // Char LCD 16x2
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| 55 | LCD_DATA,
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| 56 |
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| 57 | // AV Config
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| 58 | I2C_SDAT,
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| 59 |
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| 60 | // SD Card
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| 61 | SD_CMD,
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| 62 | SD_DAT,
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| 63 |
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| 64 | // Flash
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| 65 | FL_DQ,
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| 66 |
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| 67 | //USB
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| 68 | OTG_DATA,
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| 69 |
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| 70 | /*****************************************************************************/
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| 71 | // Outputs
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| 72 |
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| 73 | // Simple
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| 74 | LEDG,
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| 75 | LEDR,
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| 76 |
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| 77 | HEX0,
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| 78 | HEX1,
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| 79 | HEX2,
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| 80 | HEX3,
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| 81 | HEX4,
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| 82 | HEX5,
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| 83 | HEX6,
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| 84 | HEX7,
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| 85 |
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| 86 | // Memory (SRAM)
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| 87 | SRAM_ADDR,
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| 88 |
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| 89 | SRAM_CE_N,
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| 90 | SRAM_WE_N,
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| 91 | SRAM_OE_N,
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| 92 | SRAM_UB_N,
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| 93 | SRAM_LB_N,
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| 94 |
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| 95 | // Communication
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| 96 | UART_TXD,
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| 97 |
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| 98 | // Memory (SDRAM)
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| 99 | DRAM_ADDR,
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| 100 |
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| 101 | DRAM_BA,
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| 102 | DRAM_CAS_N,
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| 103 | DRAM_RAS_N,
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| 104 | DRAM_CLK,
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| 105 | DRAM_CKE,
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| 106 | DRAM_CS_N,
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| 107 | DRAM_WE_N,
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| 108 | DRAM_DQM,
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| 109 |
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| 110 | // Audio
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| 111 | AUD_XCK,
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| 112 | AUD_DACDAT,
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| 113 |
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| 114 | // VGA
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| 115 | VGA_CLK,
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| 116 | VGA_HS,
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| 117 | VGA_VS,
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| 118 | VGA_BLANK_N,
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| 119 | VGA_SYNC_N,
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| 120 | VGA_R,
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| 121 | VGA_G,
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| 122 | VGA_B,
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| 123 |
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| 124 | // Char LCD 16x2
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| 125 | LCD_ON,
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| 126 | LCD_BLON,
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| 127 | LCD_EN,
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| 128 | LCD_RS,
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| 129 | LCD_RW,
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| 130 |
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| 131 | // AV Config
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| 132 | I2C_SCLK,
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| 133 |
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| 134 | // SD Card
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| 135 | SD_CLK,
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| 136 |
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| 137 | // Flash
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| 138 | FL_ADDR,
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| 139 | FL_CE_N,
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| 140 | FL_OE_N,
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| 141 | FL_RESET_N,
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| 142 | FL_WE_N,
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| 143 |
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| 144 | // Video In
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| 145 | TD_RESET_N,
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| 146 |
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| 147 | // USB
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| 148 | OTG_ADDR,
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| 149 | OTG_CS_N,
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| 150 | OTG_OE_N,
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| 151 | OTG_RST_N,
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| 152 | OTG_WE_N,
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| 153 | );
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| 154 |
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| 155 | /*****************************************************************************
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| 156 | * Parameter Declarations *
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| 157 | *****************************************************************************/
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| 158 |
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| 159 |
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| 160 | /*****************************************************************************
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| 161 | * Port Declarations *
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| 162 | *****************************************************************************/
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| 163 |
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| 164 |
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| 165 | // Inputs
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| 166 | input CLOCK_50;
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| 167 | input TD_CLK27;
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| 168 | input [ 3: 0] KEY;
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| 169 | input [17: 0] SW;
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| 170 |
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| 171 |
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| 172 | // Communication
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| 173 | input UART_RXD;
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| 174 |
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| 175 | // Audio
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| 176 | input AUD_ADCDAT;
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| 177 |
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| 178 | // IrDA
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| 179 | input IRDA_RXD;
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| 180 |
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| 181 | // Video In
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| 182 | input [7:0] TD_DATA;
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| 183 | input TD_HS;
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| 184 | input TD_VS;
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| 185 |
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| 186 | // USB
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| 187 | input [ 1: 0] OTG_INT;
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| 188 |
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| 189 | // Bidirectionals
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| 190 | inout [35:0] GPIO;
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| 191 |
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| 192 | // Memory (SRAM)
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| 193 | inout [15: 0] SRAM_DQ;
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| 194 |
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| 195 | // Memory (SDRAM)
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| 196 | inout [31: 0] DRAM_DQ;
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| 197 |
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| 198 | // PS2 Port
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| 199 | inout PS2_KBCLK;
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| 200 | inout PS2_KBDAT;
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| 201 | inout PS2_MSCLK;
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| 202 | inout PS2_MSDAT;
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| 203 |
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| 204 | // Audio
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| 205 | inout AUD_BCLK;
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| 206 | inout AUD_ADCLRCK;
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| 207 | inout AUD_DACLRCK;
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| 208 |
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| 209 | // AV Config
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| 210 | inout I2C_SDAT;
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| 211 |
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| 212 | // Char LCD 16x2
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| 213 | inout [ 7: 0] LCD_DATA;
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| 214 |
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| 215 | // SD Card
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| 216 | inout SD_CMD;
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| 217 | inout [ 3: 0] SD_DAT;
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| 218 |
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| 219 | // Flash
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| 220 | inout [ 7: 0] FL_DQ;
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| 221 |
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| 222 | // USB
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| 223 | inout [15: 0] OTG_DATA;
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| 224 |
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| 225 | // Outputs
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| 226 | output TD_RESET_N;
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| 227 |
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| 228 | // Simple
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| 229 | output [ 8: 0] LEDG;
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| 230 | output [17: 0] LEDR;
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| 231 |
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| 232 | output [ 6: 0] HEX0;
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| 233 | output [ 6: 0] HEX1;
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| 234 | output [ 6: 0] HEX2;
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| 235 | output [ 6: 0] HEX3;
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| 236 | output [ 6: 0] HEX4;
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| 237 | output [ 6: 0] HEX5;
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| 238 | output [ 6: 0] HEX6;
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| 239 | output [ 6: 0] HEX7;
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| 240 |
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| 241 | // Memory (SRAM)
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| 242 | output [19: 0] SRAM_ADDR;
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| 243 |
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| 244 | output SRAM_CE_N;
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| 245 | output SRAM_WE_N;
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| 246 | output SRAM_OE_N;
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| 247 | output SRAM_UB_N;
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| 248 | output SRAM_LB_N;
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| 249 |
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| 250 | // Communication
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| 251 | output UART_TXD;
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| 252 |
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| 253 | // Memory (SDRAM)
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| 254 | output [12: 0] DRAM_ADDR;
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| 255 |
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| 256 | output [ 1: 0] DRAM_BA;
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| 257 | output DRAM_CAS_N;
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| 258 | output DRAM_RAS_N;
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| 259 | output DRAM_CLK;
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| 260 | output DRAM_CKE;
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| 261 | output DRAM_CS_N;
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| 262 | output DRAM_WE_N;
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| 263 | output [ 3: 0] DRAM_DQM;
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| 264 |
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| 265 | // Audio
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| 266 | output AUD_XCK;
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| 267 | output AUD_DACDAT;
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| 268 |
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| 269 | // VGA
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| 270 | output VGA_CLK;
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| 271 | output VGA_HS;
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| 272 | output VGA_VS;
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| 273 | output VGA_BLANK_N;
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| 274 | output VGA_SYNC_N;
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| 275 | output [ 7: 0] VGA_R;
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| 276 | output [ 7: 0] VGA_G;
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| 277 | output [ 7: 0] VGA_B;
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| 278 |
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| 279 | // Char LCD 16x2
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| 280 | output LCD_ON;
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| 281 | output LCD_BLON;
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| 282 | output LCD_EN;
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| 283 | output LCD_RS;
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| 284 | output LCD_RW;
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| 285 |
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| 286 | // AV Config
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| 287 | output I2C_SCLK;
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| 288 |
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| 289 | // SD Card
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| 290 | output SD_CLK;
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| 291 |
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| 292 | // Flash
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| 293 | output [22: 0] FL_ADDR;
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| 294 | output FL_CE_N;
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| 295 | output FL_OE_N;
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| 296 | output FL_RESET_N;
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| 297 | output FL_WE_N;
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| 298 |
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| 299 | //USB
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| 300 | output [ 1: 0] OTG_ADDR;
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| 301 | output OTG_CS_N;
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| 302 | output OTG_OE_N;
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| 303 | output OTG_RST_N;
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| 304 | output OTG_WE_N;
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| 305 |
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| 306 | /*****************************************************************************
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| 307 | * Internal Wires and Registers Declarations *
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| 308 | *****************************************************************************/
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| 309 | // Internal Wires
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| 310 |
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| 311 | // Internal Registers
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| 312 |
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| 313 | // State Machine Registers
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| 314 |
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| 315 | /*****************************************************************************
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| 316 | * Finite State Machine(s) *
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| 317 | *****************************************************************************/
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| 318 |
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| 319 |
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| 320 | /*****************************************************************************
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| 321 | * Sequential Logic *
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| 322 | *****************************************************************************/
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| 323 |
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| 324 |
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| 325 | /*****************************************************************************
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| 326 | * Combinational Logic *
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| 327 | *****************************************************************************/
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| 328 |
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| 329 | // Output Assignments - set GPIO safely as input.
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| 330 | assign GPIO[ 0] = 1'bZ;
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| 331 | assign GPIO[ 2] = 1'bZ;
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| 332 | assign GPIO[ 4] = 1'bZ;
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| 333 | //assign GPIO[ 6] = 1'bZ;
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| 334 |
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| 335 | /*****************************************************************************
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| 336 | * Lab2 + NIOS *
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| 337 | *****************************************************************************/
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| 338 |
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| 339 |
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| 340 |
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| 341 | wire signed [17:0]x1_output;
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| 342 | wire signed [17:0]x2_output;
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| 343 |
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| 344 | wire [10:0] kp_wire,ki_wire,kd_wire;
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| 345 |
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| 346 | ///////////////////// INSTANTIATE NIOS ///////////////////////////////////////
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| 347 |
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| 348 | nios_system NiosII (
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| 349 | // 1) global signals:
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| 350 | .clk (CLOCK_50),
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| 351 | .clk_27 (TD_CLK27),
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| 352 | .reset_n (KEY[0]),
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| 353 | .sys_clk (),
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| 354 | .vga_clk (),
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| 355 | .sdram_clk (DRAM_CLK),
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| 356 | .audio_clk (AUD_XCK),
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| 357 |
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| 358 | // the_AV_Config
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| 359 | .I2C_SDAT_to_and_from_the_AV_Config (I2C_SDAT),
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| 360 | .I2C_SCLK_from_the_AV_Config (I2C_SCLK),
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| 361 |
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| 362 | // the_SDRAM
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| 363 | .zs_addr_from_the_SDRAM (DRAM_ADDR),
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| 364 | .zs_ba_from_the_SDRAM (DRAM_BA),
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| 365 | .zs_cas_n_from_the_SDRAM (DRAM_CAS_N),
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| 366 | .zs_cke_from_the_SDRAM (DRAM_CKE),
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| 367 | .zs_cs_n_from_the_SDRAM (DRAM_CS_N),
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| 368 | .zs_dq_to_and_from_the_SDRAM (DRAM_DQ),
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| 369 | .zs_dqm_from_the_SDRAM (DRAM_DQM),
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| 370 | .zs_ras_n_from_the_SDRAM (DRAM_RAS_N),
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| 371 | .zs_we_n_from_the_SDRAM (DRAM_WE_N),
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| 372 |
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| 373 | // the_SRAM
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| 374 | .SRAM_DQ_to_and_from_the_SRAM (SRAM_DQ),
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| 375 | .SRAM_ADDR_from_the_SRAM (SRAM_ADDR),
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| 376 | .SRAM_LB_N_from_the_SRAM (SRAM_LB_N),
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| 377 | .SRAM_UB_N_from_the_SRAM (SRAM_UB_N),
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| 378 | .SRAM_CE_N_from_the_SRAM (SRAM_CE_N),
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| 379 | .SRAM_OE_N_from_the_SRAM (SRAM_OE_N),
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| 380 | .SRAM_WE_N_from_the_SRAM (SRAM_WE_N),
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| 381 |
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| 382 | .VGA_CLK_from_the_VGA_Controller (VGA_CLK),
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| 383 | .VGA_HS_from_the_VGA_Controller (VGA_HS),
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| 384 | .VGA_VS_from_the_VGA_Controller (VGA_VS),
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| 385 | .VGA_BLANK_from_the_VGA_Controller (VGA_BLANK_N),
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| 386 | .VGA_SYNC_from_the_VGA_Controller (VGA_SYNC_N),
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| 387 | .VGA_R_from_the_VGA_Controller (VGA_R),
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| 388 | .VGA_G_from_the_VGA_Controller (VGA_G),
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| 389 | .VGA_B_from_the_VGA_Controller (VGA_B),
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| 390 |
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| 391 |
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| 392 |
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| 393 | .x1_output_export(unscaled_pwm_result_from_pid_controller[15:0]),
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| 394 |
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| 395 | ////////////// EXPORT TO NIOS ///////////////////////////////////
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| 396 | //////// x2_output as Median Filter
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| 397 | .x2_output_export(median_filtered_proximity_value_to_nios),
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| 398 |
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| 399 | .kp_export (kp_wire), // kp.export
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| 400 | .ki_export (ki_wire), // ki.export
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| 401 | .kd_export (kd_wire) // kd.export
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| 402 | );
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| 403 |
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| 404 |
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| 405 |
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| 406 |
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| 407 | wire reset;
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| 408 | assign reset=~KEY[0];
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| 409 |
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| 410 | wire [15:0] median_filtered_proximity_value_to_nios;
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| 411 | wire signed [16:0] unscaled_pwm_result_from_pid_controller;
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| 412 |
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| 413 | //wire [3:0] kp, ki, kd;
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| 414 |
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| 415 |
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| 416 | spi_controller spiread (
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| 417 |
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| 418 | // INPUTS (SPI buses)
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| 419 | .cs(GPIO[0]),
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| 420 | .sck(GPIO[2]),
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| 421 | .sda(GPIO[4]),
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| 422 | .kp(kp_wire),
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| 423 | .ki(ki_wire),
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| 424 | .kd(kd_wire),
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| 425 | // OUTPUTS
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| 426 | .median_filtered_proximity_value(median_filtered_proximity_value_to_nios),
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| 427 | .unscaled_pwm_result_from_pid_controller(unscaled_pwm_result_from_pid_controller)
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| 428 | );
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| 429 |
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| 430 | pwm_output gpio_pwm_controller (
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| 431 |
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| 432 | // INPUTS
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| 433 | .clock50(CLOCK_50),
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| 434 | .switches(SW[17:0]),
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| 435 | .unscaled_pwm_result_from_pid_controller(unscaled_pwm_result_from_pid_controller),
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| 436 |
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| 437 | // OUTPUTS
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| 438 | .gpio_to_the_opamp(GPIO[35])
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| 439 | );
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| 440 |
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| 441 |
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| 442 | endmodule
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| 443 |
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| 444 | ///////////////// SPI_CONTROLLER MODULE ///////////////////////////////////
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| 445 |
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| 446 |
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| 447 | module spi_controller(cs, sck, sda, kp, ki, kd, median_filtered_proximity_value, unscaled_pwm_result_from_pid_controller);
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| 448 |
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| 449 | //////////////////////// Inputs and Outputs ////////////////////
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| 450 |
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| 451 | input cs, sck, sda;
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| 452 | input [9:0] kp, ki, kd;
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| 453 | output [15:0] median_filtered_proximity_value;
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| 454 | output signed [16:0] unscaled_pwm_result_from_pid_controller;
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| 455 |
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| 456 | //////////////////////////////////////////////////////////////
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| 457 |
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| 458 | /////////////////// SPI Transaction Registers //////////////////
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| 459 |
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| 460 | //Register used for sample storage upon positive edge of every sample clock.
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| 461 | reg [15:0] prox_out_reg;
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| 462 |
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| 463 | //Register for storage of data bits read during the SPI transaction.
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| 464 | //The proximity value is located at the 2nd and 3rd bytes of the transaction.
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| 465 | reg [47:0] raw_read_bits;
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| 466 |
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| 467 | // Proximity value history for median filter.
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| 468 | reg [15:0] prox_out1,prox_out2,prox_out3;//,prox_out4;
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| 469 |
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| 470 | //////////////////////////////////////////////////////////////
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| 471 | //////////////// Median Filter Registers /////////////////////
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| 472 |
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| 473 | reg [15:0] median_filtered_proximity_value_reg;
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| 474 |
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| 475 | //////////////////////////////////////////////////////////////
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| 476 | ///////////////// PID Registers and Paramaters ////////////////
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| 477 |
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| 478 | parameter ldc1000_setpoint = 16'd32768-16'd14800; // 32768 is MAX
|
| 479 |
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| 480 | reg signed [16:0] pid_fractional_output;
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| 481 | reg signed [16:0] pid_integral;
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| 482 | reg signed [16:0] current_error_reg;
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| 483 | reg signed [16:0] previous_error_reg;
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| 484 | reg signed [16:0] pid_integral_accumulator;
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| 485 | reg signed [16:0] unscaled_pwm_result_from_pid_controller_reg;
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| 486 | reg signed [16:0] value_test;
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| 487 |
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| 488 |
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| 489 | /////////////////////////////////////////////////////////////////
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| 490 |
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| 491 | // This is the i2c CLK. This is for every bit wise read
|
| 492 |
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| 493 | always @ (negedge sck) begin
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| 494 |
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| 495 | //Read into LSB, then shift by 1.
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| 496 | raw_read_bits[0]=sda;
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| 497 | raw_read_bits <= raw_read_bits << 1;
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| 498 |
|
| 499 | end
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| 500 |
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| 501 | // This is when CS is ready. This means that one sample is ready for us to read.
|
| 502 |
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| 503 | always @ (posedge cs) begin
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| 504 |
|
| 505 | ///////////////////////SPI READING BLOCK////////////////////
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| 506 |
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| 507 | prox_out_reg = {raw_read_bits[39:24]};
|
| 508 |
|
| 509 | // Assigning the right Median Filter Values
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| 510 | prox_out3 <= prox_out2;
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| 511 | prox_out2 <= prox_out1;
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| 512 | //We have to reverse bytes 2 and 3 because they are transmitted as {LSB,MSB}.
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| 513 | prox_out1 <= (32768-{prox_out_reg[7:0], prox_out_reg[15:8]});
|
| 514 |
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| 515 | ////////////////////////////////////////////////////////////
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| 516 |
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| 517 | //////////////////////MEDIAN FILTER BLOCK//////////////////
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| 518 |
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| 519 | // The Media Filter block reads the samples with a window size of 3 and selects the median value.
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| 520 | // This is to avoid noise spikes
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| 521 |
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| 522 | if ((prox_out1 <= prox_out2) && (prox_out1 <= prox_out3)) begin
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| 523 | median_filtered_proximity_value_reg <= ( prox_out2 <= prox_out3) ? prox_out2 : prox_out3;
|
| 524 | end
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| 525 | else if ((prox_out2 <= prox_out1) && (prox_out2<=prox_out3)) begin
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| 526 | median_filtered_proximity_value_reg <= (prox_out1 <= prox_out3) ? prox_out1 : prox_out3;
|
| 527 | end
|
| 528 | else begin
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| 529 | median_filtered_proximity_value_reg <= (prox_out1 <= prox_out2) ? prox_out1 : prox_out2;
|
| 530 | end
|
| 531 |
|
| 532 | //////////////////////////////////////////////////////////////
|
| 533 |
|
| 534 | /////////////////////PID CALCULATION STUFF///////////////////////////
|
| 535 |
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| 536 | current_error_reg <= ((ldc1000_setpoint - median_filtered_proximity_value_reg)); // This is the current error
|
| 537 |
|
| 538 | if ((current_error_reg * previous_error_reg) > 0 ) begin
|
| 539 | pid_integral_accumulator = pid_integral_accumulator + current_error_reg;
|
| 540 | end else begin
|
| 541 |
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| 542 | //pid_integral_accumulator = pid_integral_accumulator * 0.96875
|
| 543 | pid_integral_accumulator = (pid_integral_accumulator >> 1) +
|
| 544 | (pid_integral_accumulator >> 2) +
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| 545 | (pid_integral_accumulator >> 3) +
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| 546 | (pid_integral_accumulator >> 4) +
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| 547 | (pid_integral_accumulator >> 5);
|
| 548 |
|
| 549 | end
|
| 550 |
|
| 551 | value_test <= (kp * current_error_reg + ki * pid_integral + kd * (current_error_reg - previous_error_reg));
|
| 552 |
|
| 553 | if ((value_test) < 0) begin
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| 554 | unscaled_pwm_result_from_pid_controller_reg <= 0;
|
| 555 | end
|
| 556 | else if ((value_test) > 32767 ) begin
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| 557 | unscaled_pwm_result_from_pid_controller_reg <= 32767;
|
| 558 | end
|
| 559 | else begin
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| 560 | unscaled_pwm_result_from_pid_controller_reg <= value_test;
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| 561 | end
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| 562 |
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| 563 |
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| 564 | //unscaled_pwm_result_from_pid_controller_reg <= median_filtered_proximity_value_reg;
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| 565 |
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| 566 | previous_error_reg <= current_error_reg;
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| 567 |
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| 568 | /////////////////////////////////////////////////////////////////////////
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| 569 |
|
| 570 | end
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| 571 |
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| 572 | assign unscaled_pwm_result_from_pid_controller = unscaled_pwm_result_from_pid_controller_reg ;
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| 573 | assign median_filtered_proximity_value = median_filtered_proximity_value_reg;
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| 574 |
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| 575 | // We read LSB, then MSB. Now combine them together properly as {MSB,LSB}
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| 576 | // 32767 - the value, because when ball goes up, prox output should go up. It is more intuitive
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| 577 | // because prox output will change monotonically, and with same sign as height.
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| 578 | //assign prox_output = (32767-{prox_out_reg[7:0], prox_out_reg[15:8]});
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| 579 |
|
| 580 | endmodule
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| 581 |
|
| 582 | ///////////////////////////////////////////////////////////////////////////
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| 583 |
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| 584 | module pwm_output(clock50, switches, unscaled_pwm_result_from_pid_controller, gpio_to_the_opamp);
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| 585 |
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| 586 | input clock50;
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| 587 | input [17:0] switches;
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| 588 | input signed [16:0] unscaled_pwm_result_from_pid_controller;
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| 589 |
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| 590 | output gpio_to_the_opamp;
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| 591 |
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| 592 | // Variables
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| 593 | reg signed [31:0] frequency_counter;
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| 594 | reg signed [31:0] duty_cycle_counter;
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| 595 | reg signed [16:0] scaled_pwm_result_from_pid_controller;
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| 596 | reg gpio_to_the_opamp_reg;
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| 597 |
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| 598 | always @ (posedge clock50) begin
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| 599 |
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| 600 |
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| 601 | if (frequency_counter < 0 || frequency_counter == 0) begin
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| 602 |
|
| 603 | //Finished counting? Load counter back with 50 million again.
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| 604 | frequency_counter <= 32'b10111110101111000010000000;
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| 605 |
|
| 606 | //Set output = 1 because we're at the start of our cycle.
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| 607 | gpio_to_the_opamp_reg <= 1;
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| 608 |
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| 609 | //Read the PID output only at the beginning of the cycle.
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| 610 | //If the PWM value changes dynamically in the middle of the cycle, we might
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| 611 | //have some weird unwanted effects.
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| 612 |
|
| 613 | scaled_pwm_result_from_pid_controller <= unscaled_pwm_result_from_pid_controller>>7;
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| 614 |
|
| 615 | end else begin
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| 616 |
|
| 617 | //Decrement as a multiple of 5000
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| 618 | frequency_counter <= frequency_counter - ((switches[9:0]) * (32'b101));
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| 619 |
|
| 620 | //Since the PWM frequency is dependent on the switches, we can play around with
|
| 621 | // the frequency values during operation of the levitator. That way we can tell
|
| 622 | // what the optimal PWM frequency is for our application.
|
| 623 |
|
| 624 | end
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| 625 |
|
| 626 | if(scaled_pwm_result_from_pid_controller[7:0]==0) begin
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| 627 | gpio_to_the_opamp_reg <= 0;
|
| 628 | end
|
| 629 | // Replacing the switches with the output from the PID
|
| 630 | else if (frequency_counter < (32'd196078 * (255-scaled_pwm_result_from_pid_controller[7:0]))) begin
|
| 631 |
|
| 632 | //This maps to a ~0.5% to 100% duty cycle.
|
| 633 | //It will allow the FPGA to finely tune the duty cycle to whatever we need.
|
| 634 | //If we need finer tuning, we can cut "32'd196078" in half, and then we'd have a
|
| 635 | // multiplier going from 1 to 511. We can basically tune this as fine as we want it.
|
| 636 | //Probably the finer it is, the better.
|
| 637 |
|
| 638 | gpio_to_the_opamp_reg <= 0;
|
| 639 |
|
| 640 | end
|
| 641 |
|
| 642 |
|
| 643 | end
|
| 644 |
|
| 645 | assign gpio_to_the_opamp = gpio_to_the_opamp_reg;
|
| 646 |
|
| 647 | endmodule
|
