Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
The_System|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|rst_controller_001 |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
The_System|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|rst_controller |
33 |
30 |
0 |
30 |
1 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
The_System|irq_mapper_001 |
0 |
32 |
0 |
32 |
32 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
The_System|irq_mapper |
0 |
32 |
0 |
32 |
32 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
22 |
1 |
2 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|avalon_st_adapter_002 |
22 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_cmd_width_adapter|check_and_align_address_to_size |
45 |
10 |
2 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_cmd_width_adapter |
247 |
3 |
4 |
3 |
116 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_cmd_width_adapter|check_and_align_address_to_size |
45 |
10 |
2 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_cmd_width_adapter |
247 |
3 |
4 |
3 |
134 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_cmd_width_adapter|check_and_align_address_to_size |
45 |
10 |
2 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_cmd_width_adapter |
247 |
3 |
4 |
3 |
134 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_rsp_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
43 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_rsp_width_adapter |
121 |
3 |
0 |
3 |
242 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_rsp_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
43 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_rsp_width_adapter |
139 |
3 |
0 |
3 |
242 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_rsp_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
43 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_rsp_width_adapter |
139 |
3 |
0 |
3 |
242 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_mux_001|arb|adder |
12 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_mux_001|arb |
7 |
0 |
4 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_mux_001 |
726 |
0 |
0 |
0 |
244 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_mux|arb|adder |
12 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_mux|arb |
7 |
0 |
4 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_mux |
726 |
0 |
0 |
0 |
244 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_demux_002 |
245 |
4 |
2 |
4 |
483 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_demux_001 |
245 |
4 |
2 |
4 |
483 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|rsp_demux |
245 |
4 |
2 |
4 |
483 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux_002 |
485 |
0 |
0 |
0 |
243 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux_001 |
485 |
0 |
0 |
0 |
243 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_mux |
485 |
0 |
0 |
0 |
243 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_demux_001 |
248 |
9 |
2 |
9 |
724 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|cmd_demux |
248 |
9 |
2 |
9 |
724 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
39 |
0 |
2 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
38 |
5 |
0 |
5 |
31 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
118 |
0 |
0 |
0 |
116 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_burst_adapter |
118 |
0 |
0 |
0 |
116 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
39 |
0 |
2 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
38 |
5 |
0 |
5 |
32 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
136 |
0 |
0 |
0 |
134 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_burst_adapter |
136 |
0 |
0 |
0 |
134 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
21 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
20 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
39 |
0 |
2 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
38 |
5 |
0 |
5 |
32 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
136 |
0 |
0 |
0 |
134 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_burst_adapter |
136 |
0 |
0 |
0 |
134 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|arm_a9_hps_h2f_axi_master_rd_limiter |
486 |
0 |
0 |
0 |
486 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|arm_a9_hps_h2f_axi_master_wr_limiter |
486 |
0 |
0 |
0 |
486 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_004|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_004 |
115 |
0 |
2 |
0 |
116 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_003|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_003 |
133 |
0 |
2 |
0 |
134 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_002|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_002 |
133 |
0 |
2 |
0 |
134 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_001|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router_001 |
241 |
0 |
4 |
0 |
242 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|router |
241 |
0 |
4 |
0 |
242 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_agent_rdata_fifo |
63 |
41 |
0 |
41 |
20 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_agent_rsp_fifo |
155 |
39 |
0 |
39 |
114 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_agent |
274 |
22 |
24 |
22 |
301 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_agent_rsp_fifo |
173 |
39 |
0 |
39 |
132 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_agent |
342 |
39 |
40 |
39 |
372 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_agent_rsp_fifo |
173 |
39 |
0 |
39 |
132 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_agent |
342 |
39 |
40 |
39 |
372 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|arm_a9_hps_h2f_axi_master_agent|align_address_to_size |
49 |
0 |
1 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|arm_a9_hps_h2f_axi_master_agent |
787 |
197 |
335 |
197 |
640 |
197 |
197 |
197 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|sdram_s1_translator |
78 |
4 |
5 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_control_buffer_slave_translator |
113 |
6 |
18 |
6 |
79 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0|logic_analyser_0_analyzer_buffer_slave_translator |
113 |
6 |
18 |
6 |
79 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
The_System|mm_interconnect_0 |
367 |
0 |
0 |
0 |
298 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|logic_analyser_0|control_buffer |
91 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|logic_analyser_0|analyzer_buffer |
91 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|logic_analyser_0 |
156 |
25 |
0 |
25 |
97 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
The_System|hola_pll |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|system_pll|reset_from_locked |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|system_pll|sys_pll |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|system_pll |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|sdram|the_Computer_System_SDRAM_input_efifo_module |
48 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|sdram |
48 |
1 |
1 |
1 |
40 |
1 |
1 |
1 |
16 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|dll |
2 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|oct |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|c0 |
228 |
173 |
8 |
173 |
280 |
173 |
173 |
173 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|seq |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad |
7 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad |
37 |
1 |
0 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad |
19 |
1 |
0 |
1 |
3 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad |
91 |
1 |
0 |
1 |
15 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[24].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[23].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads |
118 |
0 |
5 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads |
633 |
58 |
118 |
58 |
220 |
58 |
58 |
58 |
40 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc |
10 |
0 |
1 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0|umemphy |
975 |
1 |
2 |
1 |
366 |
1 |
1 |
1 |
40 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|p0 |
878 |
545 |
0 |
545 |
130 |
545 |
545 |
545 |
40 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst|pll |
2 |
1 |
2 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border|hps_sdram_inst |
1 |
0 |
0 |
0 |
31 |
0 |
0 |
0 |
40 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io|border |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|hps_io |
12 |
0 |
0 |
0 |
46 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps|fpga_interfaces |
507 |
0 |
0 |
0 |
529 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
The_System|arm_a9_hps |
241 |
0 |
0 |
0 |
329 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
The_System |
78 |
17 |
0 |
17 |
102 |
17 |
17 |
17 |
86 |
0 |
0 |
0 |
0 |
Digit3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Digit2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Digit1 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Digit0 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |