EE 576: Laboratory 1

1-dimensional Cellular Automaton (CA).


In this assignment you will build a circuit which runs a state machine to compute and display a binary, nearest-neighbor, one-dimensional CA on a VGA monitor. The DE2 switches will be used to enter the rule number. An applet shows a display similar to what you should program. The rule number in the applet is entered by clicking boxes along the right edge of the interactive region.


  1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
  2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the evaluation board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.
  3. You will probably want to look through the VGA examples on the DE2 hardware examples page to see one way of designing a memory state machine. Notice that you need to set up the address one cycle (at 27 MHz) before you read the data. The 61LV25616 SRAM memory data sheet suggest that it requires <20 nS to set up.
  4. The default top level module for the DE2 defines all of the logical i/o signals.
  5. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
  6. You may want to use the QuartusII SignalTap tool to verify your design. Here are the steps that seem to be necssary to get SignalTap working. For more information, read the Altera tutorial on using SignalTap, an on chip logic analyzer.
    1. Choose menu Tools>SignalTap
    2. In the main SignalTap window, click Hardware Setup... (in the upper rigtht corner)
      and in the dialog box choose the hardware (USB-Blaster)
    3. Choose menu Edit>AddNodes...
      1. Choose the appropriate Filter to simplify the list of nodes, the press List
      2. Highlight nodes and move to right-hand list using > button
      3. Click OK to get back to main SignalTap window
    4. In the main SignalTap window, click the Clock ... button and choose the clock signal as in AddNodes
    5. In the node panel of the main window, set up trigger conditions.
    6. Compile and then load the design onto the FPGA
    7. In the main SignalTap window, toggle the Data/Setup button
    8. Choose menu Processing >Run Analysis


Be prepared to demo your design to your TA in lab.

Your written lab report should include:

Copyright Cornell University July 2006