EE 576: Laboratory 2
Audio spectral analysis with NiosII control.
Introduction.
In this assignment you will implement an audio filter bank controlled by a NiosII processor, then use it to analyse music or your voice. You will use the SOPC builder and QuartusII to construct a NiosII processor, QuartusII to add an audio interface, and the NiosII IDE to write a GCC program to set filter parameters and select specific filters for audio output.
Procedures:
- You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
- Make sure the Altera DE2 board is connected to power and to the PC as specified
in the evaluation board description. Turn on the power supply with the red switch
on the board. Make sure the toggle switch on the left edge of the board marked (
Run/Prog
) is in the Run
position and leave it there at all times.
The FPGA will program in the Run
position. Putting the switch in the Prog
position writes your design to flash memory, which you do not want to do.
- The default top level module for the DE2 defines all of the logical i/o signals.
- You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item
Assignments... Import Assignments...
and specifying the file name. There is no need to define pins one-by-one.
- A hardware audio interface is shown on the DE2 page. Read ADC/DAC example 5 Verilog code.
- Read the SOPC builder documentation and remember that if you use SDRAM for the NiosII, that you must include a phase-lock-loop (PLL) to time the memory.
--See also:
--Setting up a new project in the NiosII IDE:
- When using the IDE there must be no space characters in the path you choose to your workspace!
- Start the IDE and specify a workspace. When you designed the cpu and top-level module, the design was stored in a folder. In the Workspace selection dialog box, browse for that folder, then add the string
\software
to the folder path. This new folder will be used to store all of the software projects associated with the specific cpu you built in the SOPC. After you press OK, you may need to click on the workbench
icon to do anything useful.
- Create a new software project. Select
File>New>project
. A series of dialog boxes will open.
- In the
Altera NiosII item
, choose NiosII C/C++
application, then click Next
.
- Give the project a
name
, specify the ptf
file from SOPC builder, use the default location
, and specify a blank project
.
Then click Next
.
- Select
creat new system library
then click finish
.
- Back in the main IDE window, right-click on the
syslib
entry in the C/C++ Projects
pane, then select Properties
.
- In the dialog box, select
system library
on the left.
- Associate the desired device with
stdout
, stdin
, and stderr
. These will usually default to the JTAG UART.
- From the pulldown menu, select whether you are going to use
single threaded
or microC/OS
. Note that the web-version of the IDE does not support the operating system.
- Select the memory location, usually defaults to SDRAM.
- Click
OK
to proceed.
- Back in the main IDE window, right-click on the
syslib
entry in the C/C++ Projects
pane, then select Build Project
.
Wait for it to finish.
- Create header files using
File>New>headerfile
and C files using File>New>file.
The project (not the syslib) should be highlighted before creating the new source file.
- In
Run...
menu item be sure that the download option points to the actual project (not the syslib project). In the Run... dialog double-click the NiosII hardware option to find the USB-blaster device and download to the software to the NiosII.
- If you get the following message when downloading your program to the NiosII (when using SDRAM for the program):
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused>
Then some suspects come to mind:
- You forgot to assign pins to the QuartusII project.
- There is an incorrect or missing PLL file for SDRAM delay (use the megawizard
to rebuild or generate a new PLL module as described in the SDRAM tutorial.) Special Note: The component
altpll
has changed between release 7 and 8 of Quartus. When defining a PLL for the phase-shifted SDRAM clock c0
(as explained in the SDRAM tutorial), you need to add an c1
output to the PLL with zero phase-shift and use this signal for the NiosII clock! If you don't do this, the program will load normally, with no error messages, but the program will not run! A new, corrected project is zipped here.
- There is a misspelled control line in the Nios module interface, usually the clock or reset signal.
- Check the size of the compiled hardware design. If the size is less than about 2000 logic blocks, then the Nios was probably optimized away. Check all the warnings to make sure no NiosII registers were reduced.
--Opening a downloaded, zipped project from the course site
- Unzip the file.
- Open the QuartusII project then:
- Regenerate the NiosII in SPOC builder.
- Close the SOPC builder.
- Resynthesize the Verilog design.
- Download the
sof
file to the DE2.
- Start the Nios II IDE. The path to the IDE is approximately
C:\altera\kits\nios2_60\bin\eclipse\nios2-ide.exe
.
- The folder heirarchy will have a folder with all the SOPC-generated stuff in it. In that folder will be a folder entitled
software
. In the Nios II IDE menu File
, choose Switch Workspace...
and point the workspace to the software
folder. The Nios IDE will appear to close itself, then reopen in the specified workspace. Some folders should appear in the left panel of the IDE.
- In the menu
Project
, choose Clean...,
and in the dialog box choose All projects
. This action will remove any dependencies on older versions of the Nios IDE or libraries.
- Rebuild all the project parts by selecting the
Run
menu, choosing Run as...,
and then NiosII hardware
.
--Using QuartusII SignalTap tool to verify your design.
Here are the steps that seem to be necssary to get SignalTap working. For more information, read the Altera tutorial on using SignalTap, an on chip logic analyzer.
- Choose menu
Tools>SignalTap
- In the main SignalTap window, click
Hardware Setup...
(in the upper rigtht corner)
and in the dialog box choose the hardware (USB-Blaster)
- Choose menu
Edit>AddNodes...
- Choose the appropriate
Filter
to simplify the list of nodes, the press List
- Highlight nodes and move to right-hand list using
>
button
- Click
OK
to get back to main SignalTap window
- In the main SignalTap window, click the
Clock ...
button and choose the clock signal as in AddNodes
- In the node panel of the main window, set up trigger conditions.
- Compile and then load the design onto the FPGA
- In the main SignalTap window, toggle the
Data/Setup
button
- Choose menu
Processing >Run Analysis
Assignment
- You will design the cpu system, plus timers, UARTs and parallel interfaces in SOPC, then use Verilog to add the audio hardware interface. Don't use schematic entry or VHDL.
- You should implement a few dozen hardware filters spaced linearly in log(frequency). Perhaps eight 4-pole filters/octave for a minimum frequency range of 128 Hz to 4096 Hz (5 octaves) would be about right.
- You are going to need a way of debugging the filters. Perhaps displaying the energy of a few channels on the LCD display, or UART, or 7-seg LEDs would show enough information while you sweep a sine wave thorugh the frequency range.
- When all the filters are running, add the ability to sum some of them back together to form an audio signal and output it. The NIOSII console should be used to choose which filters to add. Choose a compact, understandable notation for a command language. Perhaps something like:
- C -- clears all filter output connections to audio out.
- A 1:5 -- appends filters 1 to 5 to the current output list.
- N -- stop audio out (sanity requirement) but does not clear filter list
- Y -- starts audio out but does modify filter list
- X 2:3 -- deletes filters 2 and 3 from the output list.
- The audio ouput should be the sum of all the selected filter channels (scaled for proper output) .
Be prepared to demo your design to your TA in lab.
Your written lab report should include:
- Filter frequencies and plots of filter response.
- A detailed dsecription of your SOPC design.
- A heavily commented listing of your Verilog design and GCC code.
Copyright Cornell University May 2008