ECE 5760: Laboratory 5

Design project.

For this exercise, we want you to pick a project, then design and build it. During this period there will be no other assignments, so we expect you to spend all of your time for this course on the project. You will be expected to be in lab at the usual times and to show significant progress each week of the project.

Grading:

• Grades will be assigned by rank-ordering all projects in all sections, thus you will be competing against everyone in the class for this grade.
• 20% of your project grade depends upon being prepared each week and on the quality, quantity and character of the work done during each week.
  Each week in lab a one-page progress report may be due.
• 30% depends on the project demonstration at the end of classes.
• 50% will be based on your project writeup.
• The members of a group may be graded differentially if it becomes obvious to the staff that one person is doing the bulk of the work.

When choosing a project you will need to consider availability of hardware, time available, and your programming skill. You may want to look at several of the links on the 5760 home page for project ideas.

Depends on what you will build. There are some ideas available. You should talk often to your lab instructor. You can use any combination of Verilog, SOPC, ASM, C, and an operating system. If you intend to hook hardware to the DE2 expansion connectors, you must get explicit permission.

You will be graded on several aspects of the project:

1. Appropriate level of hardware/software complexity.
2. Appropriate use of external hardware, Verilog generated hardware, assembler, C, and operating systems.
   You need not have a microcontroller instantiated on the FPGA, but many of you will.
3. A project which works according to specification (which you will write).
4. Level of effort and organization shown in lab.
5. A demonstration of the final project during the last regular scheduled lab period of the semester. The demonstration will include an explanation of your web page describing the project.
6. Completeness and understandability of the final report. The html report must be available for viewing when you do the project demo during your last regular lab period, and must be emailed to the instructor (see instructions below) at the date/time specified by the University for this class (not known until finals are announced). The web page will consist of one folder with exactly one html file with the file name index.html. In the folder there may be Verilog source files, c-source files, images, mpegs, zipped projects, or other supporting documents linked to the one html file. When posting code, you must comply with all Altera IP considerations.
   
   Documentation must include all the major sections.
   You may omit specific sections not relevant to your project:
   • Introduction
     • One sentence "sound bite" that describes your project.
     • A summary of what you did and why.
   • High level design:
     • rationale and sources of your project idea
     • background math
     • logical structure
     • hardware/software tradeoffs
     • Relationship of your design to available IEEE, ISO, ANSI, DIN, and other standards.
     • Discuss existing patents, copyrights, and trademarks which are relevant to your project.
   • Program/hardware design:
     • program details. What parts were tricky to write?
     • hardware details. Could someone else build this based on what you have written?
     • Be sure to specifically reference any design or code you used from someone else.
     • Things you tried which did not work
   • Results of the design:
     • Any and all test data, scope traces, waveforms, etc
     • speed of execution (hesitation, filcker, interactiveness, concurrency)
     • accuracy (numeric, music frequencies, video signal timing, etc)
     • how you enforced safety in the design.
     • interference with other people's designs (e.g. cpu noise, RF interference)
     • usability by you and other people
   • Conclusions:
     • Analyse your design in terms of how the results met your expectations. What might you do differently next time?
     • How did your design conform to the applicable standards?
     • Intellectual property considerations.
       • Did you reuse code or someone else's design? Did you use any of Altera's IP?
       • Did you use code in the public domain?
       • Are you reverse-engineering a design? How did you deal with patent/trademark issues?
       • Did you have to sign non-disclosure to get a sample part?
       • Are there patent opportunites for your project?
     • Legal considerations. For instance, if you use a transmitter, you must discuss the appropriate FCC legal restrictions.
   • Appendix with commented Verilog and/or program listings. When posting code, you must comply with all Altera IP considerations.
   • Appendix with schematics if you build hardware external to the DE2 board (you can download free software from expresspcb.com to draw schematics).
   • Appendix with a list of the specific tasks in the project carried out by each team member.
   • References you used:
     • Data sheets
     • Vendor sites
     • Code/designs borrowed from others
     • Background sites/paper

1. Put all of your web page files in one directory. Name this directory with the concantented netids of all the group members, e.g., brl4_rw88
   Since the pages will be on a UNIX server, you should:
   • Make sure the cases (upper/lower) of all filenames agree with their hyperlinks.
   • Use only alphanumeric characters and underscores in filenames (NO SPACES, no punctuation of any kind).
   • Check all your links to make sure they are relative to your main page.
   • Use a directory name consisting of the group's concantenated netids.
2. ZIP the directory.
3. email it to BRL4@cornell.edu. Or if it is too big, send it via dropbox at https://dropbox.cornell.edu/
4. If you submit videos to youtube, be sure to include ece5760 as a keyword for searching