//in the top-level module /////////////////// // clock divider to slow system down for testing reg [4:0] count; // analog update divided clock always @ (posedge CLOCK_50) begin count <= count + 1; end assign AnalogClock = (count==0); ///////////////////////////////////////////////// //// integrator ///////////////////////////////// ///////////////////////////////////////////////// module integrator(out,funct,InitialOut,clk,reset); output signed [26:0] out; //the state variable V input signed [26:0] funct; //the dV/dt function input clk, reset; input signed [26:0] InitialOut; //the initial state variable V wire signed [26:0] out, v1new ; reg signed [26:0] v1 ; always @ (posedge clk) begin if (reset==0) //reset v1 <= InitialOut ; // else v1 <= v1new ; end assign v1new = v1 + funct ; assign out = v1 ; endmodule ////////////////////////////////////////////////// //// signed mult of 7.20 format 2'comp//////////// ////////////////////////////////////////////////// module signed_mult (out, a, b); output signed [26:0] out; input signed [26:0] a; input signed [26:0] b; // intermediate full bit length wire signed [53:0] mult_out; assign mult_out = a * b; // select bits for 7.20 fixed point assign out = {mult_out[53], mult_out[45:20]}; endmodule //////////////////////////////////////////////////