The Quick and Dirty Guide to Using ModelSim with Quartus -- Julie Wang 2014


Modelsim is a powerful tool used to simulate Verilog or VHDL code that you have written.

This is a quick and dirty guide to getting modelsim working with Quartus. The main points are underlined and numbered. If you want more tips and tricks read the additional comments. I have tried to only include what is useful. The code for the example is here.

Step 1: Write a Testbench in Verilog/VHDL

  1. Write a testbench. Example here: testbench.v
  2. Some key components of a testbench module:
  1. timescale indicates what the length of a “tick” is and the resolution of “ticks”
  1. e.g.

        `timescale 1ns /1ps




  1. Because of `timescale 1ns/1ps, #22 will be translated to 22 ns
  2. Because of `timescale 1ns/1ps, max precision of 1ps, or .001 ns. So #22.001 will be  simulated as 22.001 ns. #22.0001 will be simulated as 22.000 ns
  3. If you want to speed up your simulation, make the resolution lower. Note you can never have a resolution that is lower than the length of the tick though
  1. Create your clocks and drive them. Don’t forget to initialize them.  Since testbenches are usually not synthesized, you can use initial blocks.
  2. Create inputs for the device under test (DUT), usually reset, play, input(s), output(s), etc.
  3. Instantiate the unit you’re testing.

Tips and Gotchas


Step 2: Connect testbench to Quartus

  1. Assignments > Settings > EDA Tool Settings > Simulation
  2. Tool name: ModelSim- Altera

        Format for output netlist: The language you wrote the testbench in. For us, Verilog HDL

        Timescale: `timescale 1ns / 1ps. The first number in `timescale directive

  1. NativeLink settings (same page)

Select Compile testbench: name of the top level module (e.g. testbench)

Add the file containing your testbench module.

  1. Set your module as the top level module, compile. Then click Tools > Run EDA Simulation Tools > EDA RTL Simulation

Tips and Gotchas



Settings Page after you have set up your testbench


Adding the testbench module and .v Verilog file


Using Modelsim:

Modelsim is a powerful tool that can be used at multiple levels. These are just a few of the things you can do with ModelSim

Adding Signals

Manipulating waveforms

Saving and loading Waveform setups

Command line functions

The real power of Modelsim lies in your ability to create .tcl scripts and run them quickly. Quartus automatically generates these, and you can play around with it. Located in: simulation/modelsim/. Example path: “C:\julie\simulation\modelsim\”.

By doing this you don’t need to recompile Quartus and run Modelsim, you can just continually edit this file and run more ModelSim simulations. It is useful though, if you are adding new modules, to just have Quartus automatically link everything up. All of the commands below can be run through the transcript window


Tips and Gotchas