Flow report for testbench
Sun Mar 16 22:44:15 2014
Quartus II Version 10.0 Build 218 06/27/2010 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Flow Summary                                                                   ;
+------------------------------------+-------------------------------------------+
; Flow Status                        ; Successful - Sun Mar 16 22:44:15 2014     ;
; Quartus II Version                 ; 10.0 Build 218 06/27/2010 SJ Full Version ;
; Revision Name                      ; testbench                                 ;
; Top-level Entity Name              ; example1                                  ;
; Family                             ; Cyclone II                                ;
; Device                             ; EP2C5F256C6                               ;
; Timing Models                      ; Final                                     ;
; Met timing requirements            ; Yes                                       ;
; Total logic elements               ; 16 / 4,608 ( < 1 % )                      ;
;     Total combinational functions  ; 16 / 4,608 ( < 1 % )                      ;
;     Dedicated logic registers      ; 16 / 4,608 ( < 1 % )                      ;
; Total registers                    ; 16                                        ;
; Total pins                         ; 20 / 158 ( 13 % )                         ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 0 / 119,808 ( 0 % )                       ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % )                            ;
; Total PLLs                         ; 0 / 2 ( 0 % )                             ;
+------------------------------------+-------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 03/16/2014 22:44:06 ;
; Main task         ; Compilation         ;
; Revision Name     ; testbench           ;
+-------------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                            ;
+--------------------------------------+---------------------------------------+---------------+-------------+----------------+
; Assignment Name                      ; Value                                 ; Default Value ; Entity Name ; Section Id     ;
+--------------------------------------+---------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID                ; 203050747514050.139502424607372       ; --            ; --          ; --             ;
; EDA_DESIGN_INSTANCE_NAME             ; NA                                    ; --            ; --          ; --             ;
; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; testbench                             ; --            ; --          ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT               ; Verilog Hdl                           ; --            ; --          ; eda_simulation ;
; EDA_SIMULATION_TOOL                  ; ModelSim-Altera (Verilog)             ; <None>        ; --          ; --             ;
; EDA_TEST_BENCH_ENABLE_STATUS         ; TEST_BENCH_MODE                       ; --            ; --          ; eda_simulation ;
; EDA_TEST_BENCH_FILE                  ; testbench.v                           ; --            ; --          ; --             ;
; EDA_TEST_BENCH_MODULE_NAME           ; testbench                             ; --            ; --          ; --             ;
; EDA_TEST_BENCH_NAME                  ; testbench                             ; --            ; --          ; eda_simulation ;
; EDA_TIME_SCALE                       ; 1 ps                                  ; --            ; --          ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP               ; 85                                    ; --            ; --          ; --             ;
; MIN_CORE_JUNCTION_TEMP               ; 0                                     ; --            ; --          ; --             ;
; PARTITION_COLOR                      ; 16764057                              ; --            ; example1    ; Top            ;
; PARTITION_FITTER_PRESERVATION_LEVEL  ; PLACEMENT_AND_ROUTING                 ; --            ; example1    ; Top            ;
; PARTITION_NETLIST_TYPE               ; SOURCE                                ; --            ; example1    ; Top            ;
; POWER_BOARD_THERMAL_MODEL            ; None (CONSERVATIVE)                   ; --            ; --          ; --             ;
; POWER_PRESET_COOLING_SOLUTION        ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --             ;
; TOP_LEVEL_ENTITY                     ; example1                              ; testbench     ; --          ; --             ;
+--------------------------------------+---------------------------------------+---------------+-------------+----------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:00:01     ; 1.0                     ; 252 MB              ; 00:00:01                           ;
; Fitter                  ; 00:00:02     ; 1.0                     ; 313 MB              ; 00:00:02                           ;
; Assembler               ; 00:00:01     ; 1.0                     ; 238 MB              ; 00:00:01                           ;
; Classic Timing Analyzer ; 00:00:00     ; 1.0                     ; 202 MB              ; 00:00:00                           ;
; EDA Netlist Writer      ; 00:00:01     ; 1.0                     ; 216 MB              ; 00:00:00                           ;
; Total                   ; 00:00:05     ; --                      ; --                  ; 00:00:04                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


+------------------------------------------------------------------------------------------+
; Flow OS Summary                                                                          ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name             ; Machine Hostname ; OS Name       ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis    ; CIT-PHILLIPS-19  ; Windows Vista ; 6.1        ; x86_64         ;
; Fitter                  ; CIT-PHILLIPS-19  ; Windows Vista ; 6.1        ; x86_64         ;
; Assembler               ; CIT-PHILLIPS-19  ; Windows Vista ; 6.1        ; x86_64         ;
; Classic Timing Analyzer ; CIT-PHILLIPS-19  ; Windows Vista ; 6.1        ; x86_64         ;
; EDA Netlist Writer      ; CIT-PHILLIPS-19  ; Windows Vista ; 6.1        ; x86_64         ;
+-------------------------+------------------+---------------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off testbench -c testbench
quartus_fit --read_settings_files=off --write_settings_files=off testbench -c testbench
quartus_asm --read_settings_files=off --write_settings_files=off testbench -c testbench
quartus_tan --read_settings_files=off --write_settings_files=off testbench -c testbench --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off testbench -c testbench



