Classic Timing Analyzer report for testbench
Sun Mar 16 22:44:13 2014
Quartus II Version 10.0 Build 218 06/27/2010 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Classic Timing Analyzer Deprecation
  3. Timing Analyzer Summary
  4. Timing Analyzer Settings
  5. Clock Settings Summary
  6. Parallel Compilation
  7. Clock Setup: 'clk'
  8. tsu
  9. tco
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



---------------------------------------
; Classic Timing Analyzer Deprecation ;
---------------------------------------
Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                      ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From         ; To           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 1.213 ns                         ; play_me      ; out[15]~reg0 ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.095 ns                         ; out[13]~reg0 ; out[13]      ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.500 ns                         ; reset        ; out[15]~reg0 ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 401.61 MHz ( period = 2.490 ns ) ; out[0]~reg0  ; out[15]~reg0 ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;              ;              ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2C5F256C6        ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                               ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From         ; To           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 401.61 MHz ( period = 2.490 ns )               ; out[0]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.276 ns                ;
; N/A   ; 411.69 MHz ( period = 2.429 ns )               ; out[1]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.215 ns                ;
; N/A   ; 413.39 MHz ( period = 2.419 ns )               ; out[0]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.145 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.144 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.134 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.109 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.074 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.073 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.063 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.038 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.003 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.003 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 2.002 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.992 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.968 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.967 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.932 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.932 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.931 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.921 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.897 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.897 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.896 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.861 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.861 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.860 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.850 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.826 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.826 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.825 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.794 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.790 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.790 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.789 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.779 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.755 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.755 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.754 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.723 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.719 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.719 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.718 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.684 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.684 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.683 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.666 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.652 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.648 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.648 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.620 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.613 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.613 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.612 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.595 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.581 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.577 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[9]~reg0  ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.560 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.559 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.549 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.542 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.542 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.524 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[10]~reg0 ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.524 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.510 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.506 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.489 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[9]~reg0  ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.489 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.488 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[5]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.478 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.471 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.471 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.453 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.453 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[10]~reg0 ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.453 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.439 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.418 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[9]~reg0  ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.418 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[11]~reg0 ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.418 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[5]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.417 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[4]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.382 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.382 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[10]~reg0 ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.382 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[12]~reg0 ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.382 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.368 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[5]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.347 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.347 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[9]~reg0  ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.347 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[11]~reg0 ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.347 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[4]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.346 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[3]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.336 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.312 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[5]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.311 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.311 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[10]~reg0 ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.311 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[12]~reg0 ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.311 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.297 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[4]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[9]~reg0  ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[11]~reg0 ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[13]~reg0 ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[3]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.275 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[2]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.265 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.241 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.241 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[4]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.240 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.240 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[10]~reg0 ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.240 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[12]~reg0 ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.240 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[3]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[5]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[9]~reg0  ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[11]~reg0 ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[13]~reg0 ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[14]~reg0 ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.205 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[2]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.204 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[1]~reg0  ; clk        ; clk      ; None                        ; None                      ; 1.194 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[5]~reg0  ; out[5]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[6]~reg0  ; out[6]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.855 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[3]~reg0  ; out[3]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.854 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[8]~reg0  ; out[8]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.854 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[10]~reg0 ; out[10]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.854 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[12]~reg0 ; out[12]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.854 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[2]~reg0  ; out[2]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[4]~reg0  ; out[4]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[7]~reg0  ; out[7]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[9]~reg0  ; out[9]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[11]~reg0 ; out[11]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[13]~reg0 ; out[13]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[14]~reg0 ; out[14]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[1]~reg0  ; out[1]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.821 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[0]~reg0  ; out[0]~reg0  ; clk        ; clk      ; None                        ; None                      ; 0.811 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; out[15]~reg0 ; out[15]~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.547 ns                ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tsu                                                                   ;
+-------+--------------+------------+---------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To           ; To Clock ;
+-------+--------------+------------+---------+--------------+----------+
; N/A   ; None         ; 1.213 ns   ; play_me ; out[15]~reg0 ; clk      ;
; N/A   ; None         ; 1.142 ns   ; play_me ; out[14]~reg0 ; clk      ;
; N/A   ; None         ; 1.071 ns   ; play_me ; out[13]~reg0 ; clk      ;
; N/A   ; None         ; 1.000 ns   ; play_me ; out[12]~reg0 ; clk      ;
; N/A   ; None         ; 0.929 ns   ; play_me ; out[11]~reg0 ; clk      ;
; N/A   ; None         ; 0.858 ns   ; play_me ; out[10]~reg0 ; clk      ;
; N/A   ; None         ; 0.787 ns   ; play_me ; out[9]~reg0  ; clk      ;
; N/A   ; None         ; 0.716 ns   ; play_me ; out[8]~reg0  ; clk      ;
; N/A   ; None         ; 0.557 ns   ; play_me ; out[7]~reg0  ; clk      ;
; N/A   ; None         ; 0.486 ns   ; play_me ; out[6]~reg0  ; clk      ;
; N/A   ; None         ; 0.415 ns   ; play_me ; out[5]~reg0  ; clk      ;
; N/A   ; None         ; 0.344 ns   ; play_me ; out[4]~reg0  ; clk      ;
; N/A   ; None         ; 0.273 ns   ; play_me ; out[3]~reg0  ; clk      ;
; N/A   ; None         ; 0.202 ns   ; play_me ; out[2]~reg0  ; clk      ;
; N/A   ; None         ; 0.131 ns   ; play_me ; out[1]~reg0  ; clk      ;
; N/A   ; None         ; -0.256 ns  ; play_me ; out[0]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[0]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[1]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[2]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[3]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[4]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[5]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[6]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[7]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[8]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[9]~reg0  ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[10]~reg0 ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[11]~reg0 ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[12]~reg0 ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[13]~reg0 ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[14]~reg0 ; clk      ;
; N/A   ; None         ; -0.270 ns  ; reset   ; out[15]~reg0 ; clk      ;
+-------+--------------+------------+---------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 7.095 ns   ; out[13]~reg0 ; out[13] ; clk        ;
; N/A   ; None         ; 6.283 ns   ; out[14]~reg0 ; out[14] ; clk        ;
; N/A   ; None         ; 6.277 ns   ; out[6]~reg0  ; out[6]  ; clk        ;
; N/A   ; None         ; 6.275 ns   ; out[2]~reg0  ; out[2]  ; clk        ;
; N/A   ; None         ; 6.264 ns   ; out[3]~reg0  ; out[3]  ; clk        ;
; N/A   ; None         ; 6.251 ns   ; out[12]~reg0 ; out[12] ; clk        ;
; N/A   ; None         ; 6.192 ns   ; out[11]~reg0 ; out[11] ; clk        ;
; N/A   ; None         ; 6.026 ns   ; out[8]~reg0  ; out[8]  ; clk        ;
; N/A   ; None         ; 6.020 ns   ; out[9]~reg0  ; out[9]  ; clk        ;
; N/A   ; None         ; 6.018 ns   ; out[4]~reg0  ; out[4]  ; clk        ;
; N/A   ; None         ; 6.015 ns   ; out[5]~reg0  ; out[5]  ; clk        ;
; N/A   ; None         ; 6.011 ns   ; out[0]~reg0  ; out[0]  ; clk        ;
; N/A   ; None         ; 5.739 ns   ; out[15]~reg0 ; out[15] ; clk        ;
; N/A   ; None         ; 5.736 ns   ; out[7]~reg0  ; out[7]  ; clk        ;
; N/A   ; None         ; 5.721 ns   ; out[1]~reg0  ; out[1]  ; clk        ;
; N/A   ; None         ; 5.718 ns   ; out[10]~reg0 ; out[10] ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+---------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To           ; To Clock ;
+---------------+-------------+-----------+---------+--------------+----------+
; N/A           ; None        ; 0.500 ns  ; reset   ; out[0]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[1]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[2]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[3]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[4]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[5]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[6]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[7]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[8]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[9]~reg0  ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[10]~reg0 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[11]~reg0 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[12]~reg0 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[13]~reg0 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[14]~reg0 ; clk      ;
; N/A           ; None        ; 0.500 ns  ; reset   ; out[15]~reg0 ; clk      ;
; N/A           ; None        ; 0.486 ns  ; play_me ; out[0]~reg0  ; clk      ;
; N/A           ; None        ; 0.099 ns  ; play_me ; out[1]~reg0  ; clk      ;
; N/A           ; None        ; 0.028 ns  ; play_me ; out[2]~reg0  ; clk      ;
; N/A           ; None        ; -0.043 ns ; play_me ; out[3]~reg0  ; clk      ;
; N/A           ; None        ; -0.114 ns ; play_me ; out[4]~reg0  ; clk      ;
; N/A           ; None        ; -0.185 ns ; play_me ; out[5]~reg0  ; clk      ;
; N/A           ; None        ; -0.256 ns ; play_me ; out[6]~reg0  ; clk      ;
; N/A           ; None        ; -0.327 ns ; play_me ; out[7]~reg0  ; clk      ;
; N/A           ; None        ; -0.486 ns ; play_me ; out[8]~reg0  ; clk      ;
; N/A           ; None        ; -0.557 ns ; play_me ; out[9]~reg0  ; clk      ;
; N/A           ; None        ; -0.628 ns ; play_me ; out[10]~reg0 ; clk      ;
; N/A           ; None        ; -0.699 ns ; play_me ; out[11]~reg0 ; clk      ;
; N/A           ; None        ; -0.770 ns ; play_me ; out[12]~reg0 ; clk      ;
; N/A           ; None        ; -0.841 ns ; play_me ; out[13]~reg0 ; clk      ;
; N/A           ; None        ; -0.912 ns ; play_me ; out[14]~reg0 ; clk      ;
; N/A           ; None        ; -0.983 ns ; play_me ; out[15]~reg0 ; clk      ;
+---------------+-------------+-----------+---------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 10.0 Build 218 06/27/2010 SJ Full Version
    Info: Processing started: Sun Mar 16 22:44:13 2014
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off testbench -c testbench --timing_analysis_only
Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 401.61 MHz between source register "out[0]~reg0" and destination register "out[15]~reg0" (period= 2.49 ns)
    Info: + Longest register to register delay is 2.276 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N1; Fanout = 3; REG Node = 'out[0]~reg0'
        Info: 2: + IC(0.307 ns) + CELL(0.393 ns) = 0.700 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 2; COMB Node = 'out[0]~17'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.771 ns; Loc. = LCCOMB_X1_Y5_N2; Fanout = 2; COMB Node = 'out[1]~19'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.842 ns; Loc. = LCCOMB_X1_Y5_N4; Fanout = 2; COMB Node = 'out[2]~21'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.913 ns; Loc. = LCCOMB_X1_Y5_N6; Fanout = 2; COMB Node = 'out[3]~23'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 0.984 ns; Loc. = LCCOMB_X1_Y5_N8; Fanout = 2; COMB Node = 'out[4]~25'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.055 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 2; COMB Node = 'out[5]~27'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.126 ns; Loc. = LCCOMB_X1_Y5_N12; Fanout = 2; COMB Node = 'out[6]~29'
        Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.285 ns; Loc. = LCCOMB_X1_Y5_N14; Fanout = 2; COMB Node = 'out[7]~31'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.356 ns; Loc. = LCCOMB_X1_Y5_N16; Fanout = 2; COMB Node = 'out[8]~33'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.427 ns; Loc. = LCCOMB_X1_Y5_N18; Fanout = 2; COMB Node = 'out[9]~35'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.498 ns; Loc. = LCCOMB_X1_Y5_N20; Fanout = 2; COMB Node = 'out[10]~37'
        Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.569 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 2; COMB Node = 'out[11]~39'
        Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.640 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 2; COMB Node = 'out[12]~41'
        Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.711 ns; Loc. = LCCOMB_X1_Y5_N26; Fanout = 2; COMB Node = 'out[13]~43'
        Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.782 ns; Loc. = LCCOMB_X1_Y5_N28; Fanout = 1; COMB Node = 'out[14]~45'
        Info: 17: + IC(0.000 ns) + CELL(0.410 ns) = 2.192 ns; Loc. = LCCOMB_X1_Y5_N30; Fanout = 1; COMB Node = 'out[15]~46'
        Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 2.276 ns; Loc. = LCFF_X1_Y5_N31; Fanout = 2; REG Node = 'out[15]~reg0'
        Info: Total cell delay = 1.969 ns ( 86.51 % )
        Info: Total interconnect delay = 0.307 ns ( 13.49 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.335 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.335 ns; Loc. = LCFF_X1_Y5_N31; Fanout = 2; REG Node = 'out[15]~reg0'
            Info: Total cell delay = 1.516 ns ( 64.93 % )
            Info: Total interconnect delay = 0.819 ns ( 35.07 % )
        Info: - Longest clock path from clock "clk" to source register is 2.335 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.335 ns; Loc. = LCFF_X1_Y5_N1; Fanout = 3; REG Node = 'out[0]~reg0'
            Info: Total cell delay = 1.516 ns ( 64.93 % )
            Info: Total interconnect delay = 0.819 ns ( 35.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "out[15]~reg0" (data pin = "play_me", clock pin = "clk") is 1.213 ns
    Info: + Longest pin to register delay is 3.584 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H1; Fanout = 2; PIN Node = 'play_me'
        Info: 2: + IC(0.615 ns) + CELL(0.414 ns) = 2.008 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 2; COMB Node = 'out[0]~17'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 2.079 ns; Loc. = LCCOMB_X1_Y5_N2; Fanout = 2; COMB Node = 'out[1]~19'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 2.150 ns; Loc. = LCCOMB_X1_Y5_N4; Fanout = 2; COMB Node = 'out[2]~21'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.221 ns; Loc. = LCCOMB_X1_Y5_N6; Fanout = 2; COMB Node = 'out[3]~23'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.292 ns; Loc. = LCCOMB_X1_Y5_N8; Fanout = 2; COMB Node = 'out[4]~25'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.363 ns; Loc. = LCCOMB_X1_Y5_N10; Fanout = 2; COMB Node = 'out[5]~27'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 2.434 ns; Loc. = LCCOMB_X1_Y5_N12; Fanout = 2; COMB Node = 'out[6]~29'
        Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 2.593 ns; Loc. = LCCOMB_X1_Y5_N14; Fanout = 2; COMB Node = 'out[7]~31'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 2.664 ns; Loc. = LCCOMB_X1_Y5_N16; Fanout = 2; COMB Node = 'out[8]~33'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 2.735 ns; Loc. = LCCOMB_X1_Y5_N18; Fanout = 2; COMB Node = 'out[9]~35'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 2.806 ns; Loc. = LCCOMB_X1_Y5_N20; Fanout = 2; COMB Node = 'out[10]~37'
        Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 2.877 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 2; COMB Node = 'out[11]~39'
        Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 2.948 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 2; COMB Node = 'out[12]~41'
        Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 3.019 ns; Loc. = LCCOMB_X1_Y5_N26; Fanout = 2; COMB Node = 'out[13]~43'
        Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 3.090 ns; Loc. = LCCOMB_X1_Y5_N28; Fanout = 1; COMB Node = 'out[14]~45'
        Info: 17: + IC(0.000 ns) + CELL(0.410 ns) = 3.500 ns; Loc. = LCCOMB_X1_Y5_N30; Fanout = 1; COMB Node = 'out[15]~46'
        Info: 18: + IC(0.000 ns) + CELL(0.084 ns) = 3.584 ns; Loc. = LCFF_X1_Y5_N31; Fanout = 2; REG Node = 'out[15]~reg0'
        Info: Total cell delay = 2.969 ns ( 82.84 % )
        Info: Total interconnect delay = 0.615 ns ( 17.16 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.335 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.335 ns; Loc. = LCFF_X1_Y5_N31; Fanout = 2; REG Node = 'out[15]~reg0'
        Info: Total cell delay = 1.516 ns ( 64.93 % )
        Info: Total interconnect delay = 0.819 ns ( 35.07 % )
Info: tco from clock "clk" to destination pin "out[13]" through register "out[13]~reg0" is 7.095 ns
    Info: + Longest clock path from clock "clk" to source register is 2.335 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.335 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 3; REG Node = 'out[13]~reg0'
        Info: Total cell delay = 1.516 ns ( 64.93 % )
        Info: Total interconnect delay = 0.819 ns ( 35.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.510 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 3; REG Node = 'out[13]~reg0'
        Info: 2: + IC(1.888 ns) + CELL(2.622 ns) = 4.510 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'out[13]'
        Info: Total cell delay = 2.622 ns ( 58.14 % )
        Info: Total interconnect delay = 1.888 ns ( 41.86 % )
Info: th for register "out[0]~reg0" (data pin = "reset", clock pin = "clk") is 0.500 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.335 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.335 ns; Loc. = LCFF_X1_Y5_N1; Fanout = 3; REG Node = 'out[0]~reg0'
        Info: Total cell delay = 1.516 ns ( 64.93 % )
        Info: Total interconnect delay = 0.819 ns ( 35.07 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.101 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_J2; Fanout = 16; PIN Node = 'reset'
        Info: 2: + IC(0.612 ns) + CELL(0.510 ns) = 2.101 ns; Loc. = LCFF_X1_Y5_N1; Fanout = 3; REG Node = 'out[0]~reg0'
        Info: Total cell delay = 1.489 ns ( 70.87 % )
        Info: Total interconnect delay = 0.612 ns ( 29.13 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 215 megabytes
    Info: Processing ended: Sun Mar 16 22:44:13 2014
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00


