Defines | |
#define | RG_BATMON (0x11) |
#define | RG_CCA_THRES (0x09) |
#define | RG_CSMA_SEED_0 (0x2d) |
#define | RG_CSMA_SEED_1 (0x2e) |
#define | RG_FTN_CTRL (0x18) |
#define | RG_IEEE_ADDR_0 (0x24) |
#define | RG_IEEE_ADDR_1 (0x25) |
#define | RG_IEEE_ADDR_2 (0x26) |
#define | RG_IEEE_ADDR_3 (0x27) |
#define | RG_IEEE_ADDR_4 (0x28) |
#define | RG_IEEE_ADDR_5 (0x29) |
#define | RG_IEEE_ADDR_6 (0x2a) |
#define | RG_IEEE_ADDR_7 (0x2b) |
#define | RG_IRQ_MASK (0x0e) |
#define | RG_IRQ_STATUS (0x0f) |
#define | RG_MAN_ID_0 (0x1e) |
#define | RG_MAN_ID_1 (0x1f) |
#define | RG_PAN_ID_0 (0x22) |
#define | RG_PAN_ID_1 (0x23) |
#define | RG_PART_NUM (0x1c) |
#define | RG_PHY_CC_CCA (0x08) |
#define | RG_PHY_ED_LEVEL (0x07) |
#define | RG_PHY_RSSI (0x06) |
#define | RG_PHY_TX_PWR (0x05) |
#define | RG_PLL_CF (0x1a) |
#define | RG_PLL_DCU (0x1b) |
#define | RG_SHORT_ADDR_0 (0x20) |
#define | RG_SHORT_ADDR_1 (0x21) |
#define | RG_TRX_CTRL_0 (0x03) |
#define | RG_TRX_STATE (0x02) |
#define | RG_TRX_STATUS (0x01) |
#define | RG_VERSION_NUM (0x1d) |
#define | RG_VREG_CTRL (0x10) |
#define | RG_XAH_CTRL (0x2c) |
#define | RG_XOSC_CTRL (0x12) |
#define RG_BATMON (0x11) |
Offset for register BATMON
#define RG_CCA_THRES (0x09) |
Offset for register CCA_THRES
#define RG_CSMA_SEED_0 (0x2d) |
Offset for register CSMA_SEED_0
#define RG_CSMA_SEED_1 (0x2e) |
Offset for register CSMA_SEED_1
#define RG_FTN_CTRL (0x18) |
Offset for register FTN_CTRL
#define RG_IEEE_ADDR_0 (0x24) |
Offset for register IEEE_ADDR_0
#define RG_IEEE_ADDR_1 (0x25) |
Offset for register IEEE_ADDR_1
#define RG_IEEE_ADDR_2 (0x26) |
Offset for register IEEE_ADDR_2
#define RG_IEEE_ADDR_3 (0x27) |
Offset for register IEEE_ADDR_3
#define RG_IEEE_ADDR_4 (0x28) |
Offset for register IEEE_ADDR_4
#define RG_IEEE_ADDR_5 (0x29) |
Offset for register IEEE_ADDR_5
#define RG_IEEE_ADDR_6 (0x2a) |
Offset for register IEEE_ADDR_6
#define RG_IEEE_ADDR_7 (0x2b) |
Offset for register IEEE_ADDR_7
#define RG_IRQ_MASK (0x0e) |
Offset for register IRQ_MASK
#define RG_IRQ_STATUS (0x0f) |
Offset for register IRQ_STATUS
#define RG_MAN_ID_0 (0x1e) |
Offset for register MAN_ID_0
#define RG_MAN_ID_1 (0x1f) |
Offset for register MAN_ID_1
#define RG_PAN_ID_0 (0x22) |
Offset for register PAN_ID_0
#define RG_PAN_ID_1 (0x23) |
Offset for register PAN_ID_1
#define RG_PART_NUM (0x1c) |
Offset for register PART_NUM
#define RG_PHY_CC_CCA (0x08) |
Offset for register PHY_CC_CCA
#define RG_PHY_ED_LEVEL (0x07) |
Offset for register PHY_ED_LEVEL
#define RG_PHY_RSSI (0x06) |
Offset for register PHY_RSSI
#define RG_PHY_TX_PWR (0x05) |
Offset for register PHY_TX_PWR
#define RG_PLL_CF (0x1a) |
Offset for register PLL_CF
#define RG_PLL_DCU (0x1b) |
Offset for register PLL_DCU
#define RG_SHORT_ADDR_0 (0x20) |
Offset for register SHORT_ADDR_0
#define RG_SHORT_ADDR_1 (0x21) |
Offset for register SHORT_ADDR_1
#define RG_TRX_CTRL_0 (0x03) |
Offset for register TRX_CTRL_0
#define RG_TRX_STATE (0x02) |
Offset for register TRX_STATE
#define RG_TRX_STATUS (0x01) |
Offset for register TRX_STATUS
#define RG_VERSION_NUM (0x1d) |
Offset for register VERSION_NUM
#define RG_VREG_CTRL (0x10) |
Offset for register VREG_CTRL
#define RG_XAH_CTRL (0x2c) |
Offset for register XAH_CTRL
#define RG_XOSC_CTRL (0x12) |
Offset for register XOSC_CTRL