Defines | |
#define | AVREG_1_75V (1) |
#define | AVREG_1_80V (0) |
#define | AVREG_1_84V (2) |
#define | AVREG_1_88V (3) |
#define | BUSY_RX (1) |
#define | BUSY_RX_AACK (17) |
#define | BUSY_RX_AACK_NOCLK (30) |
#define | BUSY_TX (2) |
#define | BUSY_TX_ARET (18) |
#define | CLKM_16MHz (5) |
#define | CLKM_1MHz (1) |
#define | CLKM_2mA (0) |
#define | CLKM_2MHz (2) |
#define | CLKM_4mA (1) |
#define | CLKM_4MHz (3) |
#define | CLKM_6mA (2) |
#define | CLKM_8mA (3) |
#define | CLKM_8MHz (4) |
#define | CLKM_no_clock (0) |
#define | CMD_FORCE_TRX_OFF (3) |
#define | CMD_NOP (0) |
#define | CMD_PLL_ON (9) |
#define | CMD_RX_AACK_ON (22) |
#define | CMD_RX_ON (6) |
#define | CMD_TRX_OFF (8) |
#define | CMD_TX_ARET_ON (25) |
#define | CMD_TX_START (2) |
#define | DVREG_1_75V (1) |
#define | DVREG_1_80V (0) |
#define | DVREG_1_84V (2) |
#define | DVREG_1_88V (3) |
#define | P_ON (0) |
#define | PLL_ON (9) |
#define | RF230 (2) |
#define | RF230_RAM_SIZE (0x80) |
#define | RSSI_BASE_VAL (-91) |
#define | RX_AACK_ON (22) |
#define | RX_AACK_ON_NOCLK (29) |
#define | RX_ON (6) |
#define | RX_ON_NOCLK (28) |
#define | SLEEP (15) |
#define | TRAC_CHANNEL_ACCESS_FAILURE (3) |
#define | TRAC_NO_ACK (5) |
#define | TRAC_SUCCESS (0) |
#define | TRX_IRQ_4 (0x10) |
#define | TRX_IRQ_5 (0x20) |
#define | TRX_IRQ_BAT_LOW (0x80) |
#define | TRX_IRQ_PLL_LOCK (0x01) |
#define | TRX_IRQ_PLL_UNLOCK (0x02) |
#define | TRX_IRQ_RX_START (0x04) |
#define | TRX_IRQ_TRX_END (0x08) |
#define | TRX_IRQ_TRX_UR (0x40) |
#define | TRX_OFF (8) |
#define | TX_ARET_ON (25) |
#define AVREG_1_75V (1) |
Constant AVREG_1_75V for sub-register SR_AVREG_TRIM
#define AVREG_1_80V (0) |
Constant AVREG_1_80V for sub-register SR_AVREG_TRIM
#define AVREG_1_84V (2) |
Constant AVREG_1_84V for sub-register SR_AVREG_TRIM
#define AVREG_1_88V (3) |
Constant AVREG_1_88V for sub-register SR_AVREG_TRIM
#define BUSY_RX (1) |
Constant BUSY_RX for sub-register SR_TRX_STATUS
#define BUSY_RX_AACK (17) |
Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS
#define BUSY_RX_AACK_NOCLK (30) |
Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS
#define BUSY_TX (2) |
Constant BUSY_TX for sub-register SR_TRX_STATUS
#define BUSY_TX_ARET (18) |
Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS
#define CLKM_16MHz (5) |
Constant CLKM_16MHz for sub-register SR_CLKM_CTRL
#define CLKM_1MHz (1) |
Constant CLKM_1MHz for sub-register SR_CLKM_CTRL
#define CLKM_2mA (0) |
Constant CLKM_2mA for sub-register SR_PAD_IO_CLKM
#define CLKM_2MHz (2) |
Constant CLKM_2MHz for sub-register SR_CLKM_CTRL
#define CLKM_4mA (1) |
Constant CLKM_4mA for sub-register SR_PAD_IO_CLKM
#define CLKM_4MHz (3) |
Constant CLKM_4MHz for sub-register SR_CLKM_CTRL
#define CLKM_6mA (2) |
Constant CLKM_6mA for sub-register SR_PAD_IO_CLKM
#define CLKM_8mA (3) |
Constant CLKM_8mA for sub-register SR_PAD_IO_CLKM
#define CLKM_8MHz (4) |
Constant CLKM_8MHz for sub-register SR_CLKM_CTRL
#define CLKM_no_clock (0) |
Constant CLKM_no_clock for sub-register SR_CLKM_CTRL
#define CMD_FORCE_TRX_OFF (3) |
Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD
#define CMD_NOP (0) |
Constant CMD_NOP for sub-register SR_TRX_CMD
#define CMD_PLL_ON (9) |
Constant CMD_PLL_ON for sub-register SR_TRX_CMD
#define CMD_RX_AACK_ON (22) |
Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD
#define CMD_RX_ON (6) |
Constant CMD_RX_ON for sub-register SR_TRX_CMD
#define CMD_TRX_OFF (8) |
Constant CMD_TRX_OFF for sub-register SR_TRX_CMD
#define CMD_TX_ARET_ON (25) |
Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD
#define CMD_TX_START (2) |
Constant CMD_TX_START for sub-register SR_TRX_CMD
#define DVREG_1_75V (1) |
Constant DVREG_1_75V for sub-register SR_DVREG_TRIM
#define DVREG_1_80V (0) |
Constant DVREG_1_80V for sub-register SR_DVREG_TRIM
#define DVREG_1_84V (2) |
Constant DVREG_1_84V for sub-register SR_DVREG_TRIM
#define DVREG_1_88V (3) |
Constant DVREG_1_88V for sub-register SR_DVREG_TRIM
#define P_ON (0) |
Constant P_ON for sub-register SR_TRX_STATUS
#define PLL_ON (9) |
Constant PLL_ON for sub-register SR_TRX_STATUS
#define RF230 (2) |
Constant RF230 for sub-register SR_PART_NUM
#define RF230_RAM_SIZE (0x80) |
RF230 FIFO size.
#define RSSI_BASE_VAL (-91) |
Minimum RSSI sensitivity value in dBm, which is equivalent to the value 0 in sub register SR_RSSI.
#define RX_AACK_ON (22) |
Constant RX_AACK_ON for sub-register SR_TRX_STATUS
#define RX_AACK_ON_NOCLK (29) |
Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS
#define RX_ON (6) |
Constant RX_ON for sub-register SR_TRX_STATUS
#define RX_ON_NOCLK (28) |
Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS
#define SLEEP (15) |
Constant SLEEP for sub-register SR_TRX_STATUS
#define TRAC_CHANNEL_ACCESS_FAILURE (3) |
Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS
#define TRAC_NO_ACK (5) |
Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS
#define TRAC_SUCCESS (0) |
Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS
#define TRX_IRQ_4 (0x10) |
reserved
#define TRX_IRQ_5 (0x20) |
reserved
#define TRX_IRQ_BAT_LOW (0x80) |
signals low battery
#define TRX_IRQ_PLL_LOCK (0x01) |
PLL goes to lock-state.
#define TRX_IRQ_PLL_UNLOCK (0x02) |
signals an unlocked PLL
#define TRX_IRQ_RX_START (0x04) |
signals begin of a receiving frame
#define TRX_IRQ_TRX_END (0x08) |
signals end of frames (transmit and receive)
#define TRX_IRQ_TRX_UR (0x40) |
signals a FIFO underrun
#define TRX_OFF (8) |
Constant TRX_OFF for sub-register SR_TRX_STATUS
#define TX_ARET_ON (25) |
Constant TX_ARET_ON for sub-register SR_TRX_STATUS