AVR Z-LINKŪ


at86rf230_registermap.h

Go to the documentation of this file.
00001 /*
00002  * This file is autogenerated from regxml2include.py
00003  * Do not modify it, changes will be lost after rebuild.
00004  */
00013 /*
00014  * Copyright (c) 2006, Atmel Corporation All rights reserved.
00015  *
00016  * Redistribution and use in source and binary forms, with or without
00017  * modification, are permitted provided that the following conditions are met:
00018  *
00019  * 1. Redistributions of source code must retain the above copyright notice,
00020  * this list of conditions and the following disclaimer.
00021  *
00022  * 2. Redistributions in binary form must reproduce the above copyright notice,
00023  * this list of conditions and the following disclaimer in the documentation
00024  * and/or other materials provided with the distribution.
00025  *
00026  * 3. The name of ATMEL may not be used to endorse or promote products derived
00027  * from this software without specific prior written permission.
00028  *
00029  * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
00030  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00031  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
00032  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
00033  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00034  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00035  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
00036  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00037  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
00038  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039  */
00046 #ifndef PHY230_REGISTERMAP_EXTERNAL_H
00047 #define PHY230_REGISTERMAP_EXTERNAL_H
00048 
00049 #define HAVE_REGISTER_MAP (1)
00050 
00053 #define RG_TRX_STATUS                    (0x01)
00054 
00057 # define SR_CCA_DONE                  0x01, 0x80, 7
00058 
00061 # define SR_CCA_STATUS                0x01, 0x40, 6
00062 # define SR_reserved_01_3             0x01, 0x20, 5
00063 
00066 # define SR_TRX_STATUS                0x01, 0x1f, 0
00067 
00070 #  define P_ON                     (0)
00071 
00074 #  define BUSY_RX                  (1)
00075 
00078 #  define BUSY_TX                  (2)
00079 
00082 #  define RX_ON                    (6)
00083 
00086 #  define TRX_OFF                  (8)
00087 
00090 #  define PLL_ON                   (9)
00091 
00094 #  define SLEEP                    (15)
00095 
00098 #  define BUSY_RX_AACK             (17)
00099 
00102 #  define BUSY_TX_ARET             (18)
00103 
00106 #  define RX_AACK_ON               (22)
00107 
00110 #  define TX_ARET_ON               (25)
00111 
00114 #  define RX_ON_NOCLK              (28)
00115 
00118 #  define RX_AACK_ON_NOCLK         (29)
00119 
00122 #  define BUSY_RX_AACK_NOCLK       (30)
00123 
00127 #define RG_TRX_STATE                     (0x02)
00128 
00131 # define SR_TRAC_STATUS               0x02, 0xe0, 5
00132 
00135 # define SR_TRX_CMD                   0x02, 0x1f, 0
00136 
00139 #  define CMD_NOP                  (0)
00140 
00143 #  define CMD_TX_START             (2)
00144 
00147 #  define CMD_FORCE_TRX_OFF        (3)
00148 
00151 #  define CMD_RX_ON                (6)
00152 
00155 #  define CMD_TRX_OFF              (8)
00156 
00159 #  define CMD_PLL_ON               (9)
00160 
00163 #  define CMD_RX_AACK_ON           (22)
00164 
00167 #  define CMD_TX_ARET_ON           (25)
00168 
00172 #define RG_TRX_CTRL_0                    (0x03)
00173 
00176 # define SR_PAD_IO                    0x03, 0xc0, 6
00177 
00180 # define SR_PAD_IO_CLKM               0x03, 0x30, 4
00181 
00184 #  define CLKM_2mA                 (0)
00185 
00188 #  define CLKM_4mA                 (1)
00189 
00192 #  define CLKM_6mA                 (2)
00193 
00196 #  define CLKM_8mA                 (3)
00197 
00200 # define SR_CLKM_SHA_SEL              0x03, 0x08, 3
00201 
00204 # define SR_CLKM_CTRL                 0x03, 0x07, 0
00205 
00208 #  define CLKM_no_clock            (0)
00209 
00212 #  define CLKM_1MHz                (1)
00213 
00216 #  define CLKM_2MHz                (2)
00217 
00220 #  define CLKM_4MHz                (3)
00221 
00224 #  define CLKM_8MHz                (4)
00225 
00228 #  define CLKM_16MHz               (5)
00229 
00233 #define RG_PHY_TX_PWR                    (0x05)
00234 
00237 # define SR_TX_AUTO_CRC_ON            0x05, 0x80, 7
00238 # define SR_reserved_05_2             0x05, 0x70, 4
00239 
00242 # define SR_TX_PWR                    0x05, 0x0f, 0
00243 
00247 #define RG_PHY_RSSI                      (0x06)
00248 # define SR_reserved_06_1             0x06, 0xe0, 5
00249 
00252 # define SR_RSSI                      0x06, 0x1f, 0
00253 
00257 #define RG_PHY_ED_LEVEL                  (0x07)
00258 
00261 # define SR_ED_LEVEL                  0x07, 0xff, 0
00262 
00266 #define RG_PHY_CC_CCA                    (0x08)
00267 
00270 # define SR_CCA_REQUEST               0x08, 0x80, 7
00271 
00274 # define SR_CCA_MODE                  0x08, 0x60, 5
00275 
00278 # define SR_CHANNEL                   0x08, 0x1f, 0
00279 
00283 #define RG_CCA_THRES                     (0x09)
00284 
00287 # define SR_CCA_CS_THRES              0x09, 0xf0, 4
00288 
00291 # define SR_CCA_ED_THRES              0x09, 0x0f, 0
00292 
00296 #define RG_IRQ_MASK                      (0x0e)
00297 
00300 # define SR_IRQ_MASK                  0x0e, 0xff, 0
00301 
00305 #define RG_IRQ_STATUS                    (0x0f)
00306 
00309 # define SR_IRQ_7_BAT_LOW             0x0f, 0x80, 7
00310 
00313 # define SR_IRQ_6_TRX_UR              0x0f, 0x40, 6
00314 
00317 # define SR_IRQ_5                     0x0f, 0x20, 5
00318 
00321 # define SR_IRQ_4                     0x0f, 0x10, 4
00322 
00325 # define SR_IRQ_3_TRX_END             0x0f, 0x08, 3
00326 
00329 # define SR_IRQ_2_RX_START            0x0f, 0x04, 2
00330 
00333 # define SR_IRQ_1_PLL_UNLOCK          0x0f, 0x02, 1
00334 
00337 # define SR_IRQ_0_PLL_LOCK            0x0f, 0x01, 0
00338 
00342 #define RG_VREG_CTRL                     (0x10)
00343 
00346 # define SR_AVREG_EXT                 0x10, 0x80, 7
00347 
00350 # define SR_AVDD_OK                   0x10, 0x40, 6
00351 
00354 # define SR_AVREG_TRIM                0x10, 0x30, 4
00355 
00358 #  define AVREG_1_80V              (0)
00359 
00362 #  define AVREG_1_75V              (1)
00363 
00366 #  define AVREG_1_84V              (2)
00367 
00370 #  define AVREG_1_88V              (3)
00371 
00374 # define SR_DVREG_EXT                 0x10, 0x08, 3
00375 
00378 # define SR_DVDD_OK                   0x10, 0x04, 2
00379 
00382 # define SR_DVREG_TRIM                0x10, 0x03, 0
00383 
00386 #  define DVREG_1_80V              (0)
00387 
00390 #  define DVREG_1_75V              (1)
00391 
00394 #  define DVREG_1_84V              (2)
00395 
00398 #  define DVREG_1_88V              (3)
00399 
00403 #define RG_BATMON                        (0x11)
00404 # define SR_reserved_11_1             0x11, 0xc0, 6
00405 
00408 # define SR_BATMON_OK                 0x11, 0x20, 5
00409 
00412 # define SR_BATMON_HR                 0x11, 0x10, 4
00413 
00416 # define SR_BATMON_VTH                0x11, 0x0f, 0
00417 
00421 #define RG_XOSC_CTRL                     (0x12)
00422 
00425 # define SR_XTAL_MODE                 0x12, 0xf0, 4
00426 
00429 # define SR_XTAL_TRIM                 0x12, 0x0f, 0
00430 
00434 #define RG_FTN_CTRL                      (0x18)
00435 
00438 # define SR_FTN_START                 0x18, 0x80, 7
00439 # define SR_reserved_18_2             0x18, 0x40, 6
00440 
00443 # define SR_FTNV                      0x18, 0x3f, 0
00444 
00448 #define RG_PLL_CF                        (0x1a)
00449 
00452 # define SR_PLL_CF_START              0x1a, 0x80, 7
00453 # define SR_reserved_1a_2             0x1a, 0x70, 4
00454 
00457 # define SR_PLL_CF                    0x1a, 0x0f, 0
00458 
00462 #define RG_PLL_DCU                       (0x1b)
00463 
00466 # define SR_PLL_DCU_START             0x1b, 0x80, 7
00467 # define SR_reserved_1b_2             0x1b, 0x40, 6
00468 
00471 # define SR_PLL_DCUW                  0x1b, 0x3f, 0
00472 
00476 #define RG_PART_NUM                      (0x1c)
00477 
00480 # define SR_PART_NUM                  0x1c, 0xff, 0
00481 
00484 #  define RF230                    (2)
00485 
00489 #define RG_VERSION_NUM                   (0x1d)
00490 
00493 # define SR_VERSION_NUM               0x1d, 0xff, 0
00494 
00498 #define RG_MAN_ID_0                      (0x1e)
00499 
00502 # define SR_MAN_ID_0                  0x1e, 0xff, 0
00503 
00507 #define RG_MAN_ID_1                      (0x1f)
00508 
00511 # define SR_MAN_ID_1                  0x1f, 0xff, 0
00512 
00516 #define RG_SHORT_ADDR_0                  (0x20)
00517 
00520 # define SR_SHORT_ADDR_0              0x20, 0xff, 0
00521 
00525 #define RG_SHORT_ADDR_1                  (0x21)
00526 
00529 # define SR_SHORT_ADDR_1              0x21, 0xff, 0
00530 
00534 #define RG_PAN_ID_0                      (0x22)
00535 
00538 # define SR_PAN_ID_0                  0x22, 0xff, 0
00539 
00543 #define RG_PAN_ID_1                      (0x23)
00544 
00547 # define SR_PAN_ID_1                  0x23, 0xff, 0
00548 
00552 #define RG_IEEE_ADDR_0                   (0x24)
00553 
00556 # define SR_IEEE_ADDR_0               0x24, 0xff, 0
00557 
00561 #define RG_IEEE_ADDR_1                   (0x25)
00562 
00565 # define SR_IEEE_ADDR_1               0x25, 0xff, 0
00566 
00570 #define RG_IEEE_ADDR_2                   (0x26)
00571 
00574 # define SR_IEEE_ADDR_2               0x26, 0xff, 0
00575 
00579 #define RG_IEEE_ADDR_3                   (0x27)
00580 
00583 # define SR_IEEE_ADDR_3               0x27, 0xff, 0
00584 
00588 #define RG_IEEE_ADDR_4                   (0x28)
00589 
00592 # define SR_IEEE_ADDR_4               0x28, 0xff, 0
00593 
00597 #define RG_IEEE_ADDR_5                   (0x29)
00598 
00601 # define SR_IEEE_ADDR_5               0x29, 0xff, 0
00602 
00606 #define RG_IEEE_ADDR_6                   (0x2a)
00607 
00610 # define SR_IEEE_ADDR_6               0x2a, 0xff, 0
00611 
00615 #define RG_IEEE_ADDR_7                   (0x2b)
00616 
00619 # define SR_IEEE_ADDR_7               0x2b, 0xff, 0
00620 
00624 #define RG_XAH_CTRL                      (0x2c)
00625 
00628 # define SR_MAX_FRAME_RETRIES         0x2c, 0xf0, 4
00629 
00632 # define SR_MAX_CSMA_RETRIES          0x2c, 0x0e, 1
00633 # define SR_reserved_2c_3             0x2c, 0x01, 0
00634 
00638 #define RG_CSMA_SEED_0                   (0x2d)
00639 
00642 # define SR_CSMA_SEED_0               0x2d, 0xff, 0
00643 
00647 #define RG_CSMA_SEED_1                   (0x2e)
00648 
00651 # define SR_MIN_BE                    0x2e, 0xc0, 6
00652 # define SR_reserved_2e_2             0x2e, 0x30, 4
00653 
00656 # define SR_I_AM_COORD                0x2e, 0x08, 3
00657 
00660 # define SR_CSMA_SEED_1               0x2e, 0x07, 0
00661 
00662 #endif /* PHY230_REGISTERMAP_EXTERNAL_H */
@DOC_TITLE@
Generated on Wed Jul 11 18:16:31 2007 for AVR2001 AT86RF230 Software Programmer's Manual by doxygen 1.4.7