The following state transitions are defined:
trx_bit_write(SR_TRX_CMD, CMD_PLL_ON); delay_us(180); /* TRX_IRQ_PLL_LOCK occurs within this period */ trxstat = trx_bit_read(SR_TRX_STATUS); ASSERT(trxstat==PLL_ON);
trx_bit_write(SR_TRX_CMD, CMD_PLL_ON); delay_us(1); trxstat = trx_bit_read(SR_TRX_STATUS); ASSERT(trxstat==PLL_ON);
trx_bit_write(SR_TRX_CMD, CMD_PLL_ON); /* TRX_IRQ_TRX_END occurs here */ delay_us(1); trxstat = trx_bit_read(SR_TRX_STATUS); ASSERT(trxstat==PLL_ON);
trx_bit_write(SR_TRX_CMD, CMD_PLL_ON); delay_us(4256); trxstat = trx_bit_read(SR_TRX_STATUS); ASSERT(trxstat==PLL_ON);