Continuous Transmission Test Mode

This section describes, how the radio transceiver can be forced to transmit a continuous PRBS or CW signal, which can be used for RF related measurements and other test purposes.

Note:
The functionality of the Continuous Transmit Mode is not characterized by Atmel and therefore not guaranteed. The normal operation of the AT86RF230 is only guaranteed if pin TST is always logic low.
Parameters:
txcwdata array of random data, which is permanently sent out. It is recommended, that the array has a length of 127, which is the maximum possible framesize, which can be stored in the SRAM of the radio transceiver. If the synchronisation header (SHR: 0,0,0,0,0xA7) is included in this array, and PRBS mode is selected, the continuous transmission can be recognized as a loop of individual 802.15.4-2003 frames without interframe spacing.
txcwmode Select the mode of the continuous tranmission
  • 0x00: PRBS signal, modulated signal
  • 0x10: CW signal, -2.0MHz relative to channel center frequency
  • 0x80: CW signal, -0.5MHz relative to channel center frequency
  • 0xC0: CW signal, +0.5MHz relative to channel center frequency
Additionaly to these parameters, the current channel (see PHY_SET_CHANNEL) and transmit power (see PHY_SET_TRANSMIT_POWER) of the radio transceiver can be configured before starting the continuous transmit operation.

Note:
For Continuous Transmit Mode the bit SR_TX_AUTO_CRC_ON shall be set to 0.
The following sequences are defined:


PHY_START_CONT_TX

inline_mscgraph_72
Code example
    trxstat = trx_bit_read(SR_TRX_STATUS);
    ASSERT(trxstat==TRX_OFF);
    trx_bit_write(SR_TX_AUTO_CRC_ON, 0);
    trx_frame_write(len(txcwdata), txcwdata);
    trx_reg_write(0x36, 15);
    trx_reg_write(0x3d, txcwmode);
    trx_pinset_tst(1);
    trx_bit_write(SR_TRX_CMD, CMD_PLL_ON);
    delay_us(180); /* TRX_IRQ_PLL_LOCK occurs within this period */
    trx_bit_write(SR_TRX_CMD, CMD_TX_START);

PHY_STOP_CONT_TX

To stop a continuous wave transmission, the control pin TRX_PIN_TST is set to low level and a chip reset is performed (see also PHY_RESET).

inline_mscgraph_73
Code example

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