Defines | |
#define | SR_AVDD_OK 0x10, 0x40, 6 |
#define | SR_AVREG_EXT 0x10, 0x80, 7 |
#define | SR_AVREG_TRIM 0x10, 0x30, 4 |
#define | SR_BATMON_HR 0x11, 0x10, 4 |
#define | SR_BATMON_OK 0x11, 0x20, 5 |
#define | SR_BATMON_VTH 0x11, 0x0f, 0 |
#define | SR_CCA_CS_THRES 0x09, 0xf0, 4 |
#define | SR_CCA_DONE 0x01, 0x80, 7 |
#define | SR_CCA_ED_THRES 0x09, 0x0f, 0 |
#define | SR_CCA_MODE 0x08, 0x60, 5 |
#define | SR_CCA_REQUEST 0x08, 0x80, 7 |
#define | SR_CCA_STATUS 0x01, 0x40, 6 |
#define | SR_CHANNEL 0x08, 0x1f, 0 |
#define | SR_CLKM_CTRL 0x03, 0x07, 0 |
#define | SR_CLKM_SHA_SEL 0x03, 0x08, 3 |
#define | SR_CSMA_SEED_0 0x2d, 0xff, 0 |
#define | SR_CSMA_SEED_1 0x2e, 0x07, 0 |
#define | SR_DVDD_OK 0x10, 0x04, 2 |
#define | SR_DVREG_EXT 0x10, 0x08, 3 |
#define | SR_DVREG_TRIM 0x10, 0x03, 0 |
#define | SR_ED_LEVEL 0x07, 0xff, 0 |
#define | SR_FTN_START 0x18, 0x80, 7 |
#define | SR_FTNV 0x18, 0x3f, 0 |
#define | SR_I_AM_COORD 0x2e, 0x08, 3 |
#define | SR_IEEE_ADDR_0 0x24, 0xff, 0 |
#define | SR_IEEE_ADDR_1 0x25, 0xff, 0 |
#define | SR_IEEE_ADDR_2 0x26, 0xff, 0 |
#define | SR_IEEE_ADDR_3 0x27, 0xff, 0 |
#define | SR_IEEE_ADDR_4 0x28, 0xff, 0 |
#define | SR_IEEE_ADDR_5 0x29, 0xff, 0 |
#define | SR_IEEE_ADDR_6 0x2a, 0xff, 0 |
#define | SR_IEEE_ADDR_7 0x2b, 0xff, 0 |
#define | SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 |
#define | SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 |
#define | SR_IRQ_2_RX_START 0x0f, 0x04, 2 |
#define | SR_IRQ_3_TRX_END 0x0f, 0x08, 3 |
#define | SR_IRQ_4 0x0f, 0x10, 4 |
#define | SR_IRQ_5 0x0f, 0x20, 5 |
#define | SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 |
#define | SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 |
#define | SR_IRQ_MASK 0x0e, 0xff, 0 |
#define | SR_MAN_ID_0 0x1e, 0xff, 0 |
#define | SR_MAN_ID_1 0x1f, 0xff, 0 |
#define | SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 |
#define | SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 |
#define | SR_MIN_BE 0x2e, 0xc0, 6 |
#define | SR_PAD_IO 0x03, 0xc0, 6 |
#define | SR_PAD_IO_CLKM 0x03, 0x30, 4 |
#define | SR_PAN_ID_0 0x22, 0xff, 0 |
#define | SR_PAN_ID_1 0x23, 0xff, 0 |
#define | SR_PART_NUM 0x1c, 0xff, 0 |
#define | SR_PLL_CF 0x1a, 0x0f, 0 |
#define | SR_PLL_CF_START 0x1a, 0x80, 7 |
#define | SR_PLL_DCU_START 0x1b, 0x80, 7 |
#define | SR_PLL_DCUW 0x1b, 0x3f, 0 |
#define | SR_RSSI 0x06, 0x1f, 0 |
#define | SR_SHORT_ADDR_0 0x20, 0xff, 0 |
#define | SR_SHORT_ADDR_1 0x21, 0xff, 0 |
#define | SR_TRAC_STATUS 0x02, 0xe0, 5 |
#define | SR_TRX_CMD 0x02, 0x1f, 0 |
#define | SR_TRX_STATUS 0x01, 0x1f, 0 |
#define | SR_TX_AUTO_CRC_ON 0x05, 0x80, 7 |
#define | SR_TX_PWR 0x05, 0x0f, 0 |
#define | SR_VERSION_NUM 0x1d, 0xff, 0 |
#define | SR_XTAL_MODE 0x12, 0xf0, 4 |
#define | SR_XTAL_TRIM 0x12, 0x0f, 0 |
#define SR_AVDD_OK 0x10, 0x40, 6 |
Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL
#define SR_AVREG_EXT 0x10, 0x80, 7 |
Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL
#define SR_AVREG_TRIM 0x10, 0x30, 4 |
Access parameters for sub-register AVREG_TRIM in register RG_VREG_CTRL
#define SR_BATMON_HR 0x11, 0x10, 4 |
Access parameters for sub-register BATMON_HR in register RG_BATMON
#define SR_BATMON_OK 0x11, 0x20, 5 |
Access parameters for sub-register BATMON_OK in register RG_BATMON
#define SR_BATMON_VTH 0x11, 0x0f, 0 |
Access parameters for sub-register BATMON_VTH in register RG_BATMON
#define SR_CCA_CS_THRES 0x09, 0xf0, 4 |
Access parameters for sub-register CCA_CS_THRES in register RG_CCA_THRES
#define SR_CCA_DONE 0x01, 0x80, 7 |
Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS
#define SR_CCA_ED_THRES 0x09, 0x0f, 0 |
Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES
#define SR_CCA_MODE 0x08, 0x60, 5 |
Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA
#define SR_CCA_REQUEST 0x08, 0x80, 7 |
Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA
#define SR_CCA_STATUS 0x01, 0x40, 6 |
Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS
#define SR_CHANNEL 0x08, 0x1f, 0 |
Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA
#define SR_CLKM_CTRL 0x03, 0x07, 0 |
Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0
#define SR_CLKM_SHA_SEL 0x03, 0x08, 3 |
Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0
#define SR_CSMA_SEED_0 0x2d, 0xff, 0 |
Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0
#define SR_CSMA_SEED_1 0x2e, 0x07, 0 |
Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1
#define SR_DVDD_OK 0x10, 0x04, 2 |
Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL
#define SR_DVREG_EXT 0x10, 0x08, 3 |
Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL
#define SR_DVREG_TRIM 0x10, 0x03, 0 |
Access parameters for sub-register DVREG_TRIM in register RG_VREG_CTRL
#define SR_ED_LEVEL 0x07, 0xff, 0 |
Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL
#define SR_FTN_START 0x18, 0x80, 7 |
Access parameters for sub-register FTN_START in register RG_FTN_CTRL
#define SR_FTNV 0x18, 0x3f, 0 |
Access parameters for sub-register FTNV in register RG_FTN_CTRL
#define SR_I_AM_COORD 0x2e, 0x08, 3 |
Access parameters for sub-register I_AM_COORD in register RG_CSMA_SEED_1
#define SR_IEEE_ADDR_0 0x24, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0
#define SR_IEEE_ADDR_1 0x25, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1
#define SR_IEEE_ADDR_2 0x26, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2
#define SR_IEEE_ADDR_3 0x27, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3
#define SR_IEEE_ADDR_4 0x28, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4
#define SR_IEEE_ADDR_5 0x29, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5
#define SR_IEEE_ADDR_6 0x2a, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6
#define SR_IEEE_ADDR_7 0x2b, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7
#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 |
Access parameters for sub-register IRQ_0_PLL_LOCK in register RG_IRQ_STATUS
#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 |
Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS
#define SR_IRQ_2_RX_START 0x0f, 0x04, 2 |
Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS
#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 |
Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS
#define SR_IRQ_4 0x0f, 0x10, 4 |
Access parameters for sub-register IRQ_4 in register RG_IRQ_STATUS
#define SR_IRQ_5 0x0f, 0x20, 5 |
Access parameters for sub-register IRQ_5 in register RG_IRQ_STATUS
#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 |
Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS
#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 |
Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS
#define SR_IRQ_MASK 0x0e, 0xff, 0 |
Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK
#define SR_MAN_ID_0 0x1e, 0xff, 0 |
Access parameters for sub-register MAN_ID_0 in register RG_MAN_ID_0
#define SR_MAN_ID_1 0x1f, 0xff, 0 |
Access parameters for sub-register MAN_ID_1 in register RG_MAN_ID_1
#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 |
Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL
#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 |
Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL
#define SR_MIN_BE 0x2e, 0xc0, 6 |
Access parameters for sub-register MIN_BE in register RG_CSMA_SEED_1
#define SR_PAD_IO 0x03, 0xc0, 6 |
Access parameters for sub-register PAD_IO in register RG_TRX_CTRL_0
#define SR_PAD_IO_CLKM 0x03, 0x30, 4 |
Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0
#define SR_PAN_ID_0 0x22, 0xff, 0 |
Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0
#define SR_PAN_ID_1 0x23, 0xff, 0 |
Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1
#define SR_PART_NUM 0x1c, 0xff, 0 |
Access parameters for sub-register PART_NUM in register RG_PART_NUM
#define SR_PLL_CF 0x1a, 0x0f, 0 |
Access parameters for sub-register PLL_CF in register RG_PLL_CF
#define SR_PLL_CF_START 0x1a, 0x80, 7 |
Access parameters for sub-register PLL_CF_START in register RG_PLL_CF
#define SR_PLL_DCU_START 0x1b, 0x80, 7 |
Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU
#define SR_PLL_DCUW 0x1b, 0x3f, 0 |
Access parameters for sub-register PLL_DCUW in register RG_PLL_DCU
#define SR_RSSI 0x06, 0x1f, 0 |
Access parameters for sub-register RSSI in register RG_PHY_RSSI
#define SR_SHORT_ADDR_0 0x20, 0xff, 0 |
Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0
#define SR_SHORT_ADDR_1 0x21, 0xff, 0 |
Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1
#define SR_TRAC_STATUS 0x02, 0xe0, 5 |
Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE
#define SR_TRX_CMD 0x02, 0x1f, 0 |
Access parameters for sub-register TRX_CMD in register RG_TRX_STATE
#define SR_TRX_STATUS 0x01, 0x1f, 0 |
Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS
#define SR_TX_AUTO_CRC_ON 0x05, 0x80, 7 |
Access parameters for sub-register TX_AUTO_CRC_ON in register RG_PHY_TX_PWR
#define SR_TX_PWR 0x05, 0x0f, 0 |
Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR
#define SR_VERSION_NUM 0x1d, 0xff, 0 |
Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM
#define SR_XTAL_MODE 0x12, 0xf0, 4 |
Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL
#define SR_XTAL_TRIM 0x12, 0x0f, 0 |
Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL