| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u_wishbone_arbiter |
415 |
0 |
0 |
0 |
636 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| main_mem32.u_main_mem|u_main_mem|altsyncram_component|auto_generated |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| main_mem32.u_main_mem|u_main_mem |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| main_mem32.u_main_mem |
72 |
1 |
21 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_interrupt_controller |
80 |
1 |
21 |
1 |
36 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_timer_module |
72 |
1 |
37 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_test_module |
72 |
1 |
21 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_uart1 |
74 |
3 |
45 |
3 |
35 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_uart0 |
74 |
2 |
45 |
2 |
36 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| boot_mem32.u_boot_mem|u_mem|altsyncram_component|auto_generated |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| boot_mem32.u_boot_mem|u_mem |
50 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| boot_mem32.u_boot_mem |
72 |
1 |
21 |
1 |
34 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_coprocessor |
95 |
0 |
14 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_execute|u_register_bank |
102 |
8 |
0 |
8 |
160 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_execute|u_multiply |
69 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_execute|u_alu |
75 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_execute|u_barrel_shift |
44 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_execute |
208 |
24 |
16 |
24 |
171 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_decode |
112 |
10 |
24 |
10 |
276 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_wishbone |
108 |
0 |
36 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[3].u_data|u_data_mem|altsyncram_component|auto_generated |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[3].u_data|u_data_mem |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[3].u_data |
154 |
16 |
0 |
16 |
128 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[3].u_tag|u_tag_mem|altsyncram_component|auto_generated |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[3].u_tag|u_tag_mem |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[3].u_tag |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[2].u_data|u_data_mem|altsyncram_component|auto_generated |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[2].u_data|u_data_mem |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[2].u_data |
154 |
16 |
0 |
16 |
128 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[2].u_tag|u_tag_mem|altsyncram_component|auto_generated |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[2].u_tag|u_tag_mem |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[2].u_tag |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[1].u_data|u_data_mem|altsyncram_component|auto_generated |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[1].u_data|u_data_mem |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[1].u_data |
154 |
16 |
0 |
16 |
128 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[1].u_tag|u_tag_mem|altsyncram_component|auto_generated |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[1].u_tag|u_tag_mem |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[1].u_tag |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[0].u_data|u_data_mem|altsyncram_component|auto_generated |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[0].u_data|u_data_mem |
154 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[0].u_data |
154 |
16 |
0 |
16 |
128 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[0].u_tag|u_tag_mem|altsyncram_component|auto_generated |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[0].u_tag|u_tag_mem |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache|rams[0].u_tag |
31 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch|u_cache |
172 |
0 |
24 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_amber|u_fetch |
175 |
2 |
1 |
2 |
104 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_amber |
38 |
0 |
0 |
0 |
71 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_clocks_resets|u_sys_pll|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_clocks_resets|u_sys_pll |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_clocks_resets |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |