Yi-Hsiang (Sean) Lai

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I am currently a Ph.D. student at Cornell's Computer System Lab under Zhiru Zhang's advice since 2016. I received my bachelor's degree in Electrical Engineering from National Taiwan University in 2013 and my master's degree in Electronics Engineering from National Taiwan University in 2015 under Jie-Hong Roland Jiang's advice. My area of interest includes but is not limited to electronic design automation (EDA), high-level synthesis (HLS), domain-specific languages (DSL), and machine learning.

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Publications (Google Scholar)

  • Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher Hughes, Pradeep Dubey: SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020
  • Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang: HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing (Best Paper Award). FPGA 2019
  • Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang: Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. FPGA 2018
  • Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang: Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. TCAD 2016
  • Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang: Analytic Approaches to the Collapse Operation and Equivalence Verification of Threshold Logic Circuits. ICCAD 2016
  • Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang: Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. ICCAD 2015
  • Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang: SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. ICCAD 2015
  • Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang: A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. ICCAD 2015
  • Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang: Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. DAC 2014