Using IP Library
with DE1-SoC
Cornell ece5760

Library Overview

The Quartus Prime software installation includes the Intel FPGA IP library (1). The library alllows you to specify in detail how your Verilog should map to specific hardware on the FPGA. For instance, there is support for several types on memory which can be mapped to Logic Elements, or MLAB, or M10K blocks. You can find the installed IP Catalog on the menu ( Tools ➤ IP Catalog ) to efficiently parameterize and generate synthesis and simulation files for your custom IP variation (2). Each different IP core has a users guide with all the details you need to make it work. Generally, you navigate a series of dialog boxes to set up the core, then include the generated module in your project, and instatiate it in the top-level module.
The Intel FPGA IP library includes the following types of IP cores:

OpenCL

A higher level interface to the FPGA is being developed which is consistent with the OpenCL 1.0 standard.

DE1-SoC OpenCL users manual from Terasic page

Intel/Altera OpenCL programming guide


References

(1) IP libarary Intro

(2) Intel/Altera IP page

 


Copyright Cornell University February 9, 2017