FPGA Ray Tracer
Scott Bingham / Donald Zhang

| Introduction | High Level Design | Program/Hardware Design | Results | Conclusion | Appendix |


Overall, our ray tracer performed much better than expected. We believe our renderings look very impressive. By using spheres and planes, we can create very impressive scenes, especially with high levels of reflections and anti-aliasing. Because we used nearly every logic element on the FPGA, we were unable to instantiate multiple tracers or pipeline our giant state machine. This severely limited our frame rate; however, drawing a few bouncing spheres on the 320x240 resolution with 4x anti-aliasing and full reflections still ran at a reasonable rate. We felt that adding anti-aliasing, reflections, and planes were a better use of the hardware resources than pipelining our design, and the realistic renderings we were able to produce support this. While the tracer draws slowly on the complicated scenes with many objects, there are no visible artifacts on the screen.

Another feature we tried to add but wasn't successful was to have the DE2 board interface with a PS/2 mouse, and use the mouse to control the rotation of the camera view instead of using switches. This should have been a very simple design to implement. However the DE2 board and the manual gave conflicting information on whether if it can actually interface with a mouse. When we tried to connect a mouse to the DE2 board it showed no sign of detecting any hardware, while when a keyboard is pluged in it worked fine.

In this lab we learnt a great deal about ray tracing and programing FPGA as well as NIOS II in general. Another important aspect of this project is doing fixed point arthmetic in FPGA. We also pushed the FPGA to its limit as far as number of logic elements go in our final design. There is room to optimize both for speed and size in our design for future work.

Future Work:
-Add triangular polygon detection to the plane hardware
-Use multiple FPGA's to increase frame rate
-Pipeline the design on a larger FPGA to increase frame rate